[Asterisk-Dev] Asterisk Hardware Platform - Intel x86 versus
Intel RISC Xscale (ARM)
Holger Schurig
hs4233 at mail.mn-solutions.de
Fri Nov 26 02:10:51 MST 2004
> HS> One thing that is always an issue with a RISC type chip is
> HS> alignment. You might need to adjust your source code to get
> HS> alignment correct.
>
> Can you clarify this?
When you have a memory structure like this:
+---------+
| byte | 00
+---------+
| | 01
+ +
| | 02
+ long +
| | 03
+ +
| | 04
+---------+
then a x86 (or CISC) chip can access the 32 bit value with some penalty,
but it can access it.
However, ARM chips (and Intel XScale is a sub-architecture of ARM) and
some other RISC chips can't access that. They can only fetch data from 32
bit boundaries. Therefore, the processor throws an exception.
The arm-version of the Linux kernel can catch this exception, use two 32
bit accesses to get the 32 bit long. Then they assemble the data and
return from the exception.
Unfortunately, this takes an awful lot of time.
Usually this happens only when you have external things force you to have
this layout, e.g. it happened for me in fdisk (because of the layout of
the MBR sector) or in libusb. Here, the format of some USB urb's had this
weird alignment.
So, it's rare, but it happens. In your own programs, it usually doesn't
happen, because you do either:
+---------+
| | 00
+ +
| | 01
+ long +
| | 02
+ +
| | 03
+---------+
| byte | 04
+---------+
or
+---------+
| byte | 00
+---------+
| <empty> | 01
+---------+
| <empty> | 02
+---------+
| <empty> | 03
+---------+
| | 04
+ +
| | 05
+ long +
| | 06
+ +
| | 07
+---------+
The latter is the default behavior of arm-linux-gcc.
There is some iaxclient based Phone software for ARM based PDAs available
and they this alignment problem in the IAX protocol. Eventually a patch
made it into iaxclient so that the assembly of the 32 bit long value was
done in user-space, not in kernel, which is quite faster.
And because this was necessary in iaxclient, I think it will bite you in
Asterisk as well.
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