[Asterisk-Users] Asterisk - fax - spandsp

[Peter Svensson]

On Mon, 16 May 2005, Michael Welter wrote:

> Where is the clock source that the T1/E1 board, with "0" for timing, 
> uses to generate the tx data stream?  Is there a PLL on each board?  Or 
> is some central source used?
> 
> For example, I have one system with two separate T100P cards--one for a 
> telco T-1 (#1) and the other for a channel bank (#2).  For timing, #1 
> (telco) is set to "1" and #2 (channel bank) is set to "0".  How does 
> card #2 get its timing to generate its tx stream?  Does card #1 
> interrupt the CPU based on the retrieved clock stream, and the CPU drive 
> the other boards based on #1's interrupts?

The #1 card will derive its clock from the received stream from the telco. 
The #2 card will run on an internal free running clock. The two cards are 
not synchronized at all. 

For the 4-port cards there is an unused connector marked "timing". Perhaps 
Digium intends to update the fpga to allow cross-board timing 
distribution at a later date.

It is possible, though complicated, to synchronize the 2Mbit clocks on two 
unrelated cards by measuring the accumulated phase shift (difference in 
interrupt rate) over time and compensating, thus implementing a PLL in 
software. Digium has not shown any intereset in such a solution. It is not 
clear if the internal hardware clock generator can be fine tuned enough to 
implement this.

Peter