[asterisk-dev] Makefile.rules MAKE_DEPS usage

Luigi Rizzo rizzo at iet.unipi.it
Sat Dec 5 09:49:18 CST 2009

while trying to build asterisk with a non-gcc compiler, i
noticed that the build code make only a single pass to build
objects and dependency files, and always uses $(MAKE_DEPS)
to invoke the compiler, see Makefile.rules:

    # extra cflags to build dependencies. Recursively expanded.
    MAKE_DEPS=-MD -MT $@ -MF .$(subst /,_,$@).d -MP


    %.o: %.c
        $(ECHO_PREFIX) echo "   [CC] $< -> $@"
        $(CMD_PREFIX) $(CC) -o $@ -c $< $(MAKE_DEPS) $(CC_CFLAGS)

This means that the .*.d files are always updated while
building an object, which in turn implies that the build might
miss some dependency.

It would be better (in the long term) to modify the makefiles
so there is an explicit .depend target which just runs the -M part

    MAKE_DEPS=-M -MT $@ -MF .$(subst /,_,$@).d -MP


and then a second pass (which uses the new .*.d )
to do the actual code generation without $(MAKE_DEPS).

For those curious why I hit this:
i am trying to build asterisk with tcc (Fabrice Bellard's tcc --
see http://bellard.org/tcc/ ) which is supposed to be 10 times
faster than gcc 3.2 (which probably means 20 times faster than gcc
4.3.x) -- a big timesaver when doing development.

There are some small missing features in tcc (such as -M and friends)
but those were trivial to implement as long as you don't also need
to do the code generation at the same time.

To have both -M and code at the same time i need to run the compiler
twice, which is still fast and easy (a one-line change in Makefile.rules),
so this is not a showstopper.


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