[Asterisk-Dev] About OpenSS7 integration to Asterisk

[Paul Cadach]

Hi,

----- Original Message -----
From: "Storer, Darren" <stardev at comgate.tv>
To: "Asterisk-Dev at Lists. Digium. Com" <asterisk-dev at lists.digium.com>
Sent: Friday, May 07, 2004 4:21 PM
Subject: Re: [Asterisk-Dev] About OpenSS7 integration to Asterisk


[skipped]

> BFGB> "Asterisk soft-HDLC code could not handle SS7 (FISUs and
> BFGB> LSSUs), was putting too many flags between frames, was
> BFGB> discarding frames, wrapping on the receive buffers, ...
> BFGB> It would not be possible to meet 10E-6 BER because the
> BFGB> Asterisk soft-HDLC was introducing more errors than that
> BFGB> leaving nothing for the transmission facility.  Skips and
> BFGB> drops and pops might be ok for voice and even line-side
> BFGB> ISDN signalling, but is unacceptable for trunk-side
> BFGB> transmission and signalling."
>
> It would be wonderful to see cost effective SS7 (especially INAP) solutions
> but the requirements for timing usually mean that more expensive
> "intelligent" line cards must be used, not to mention the cost of SS7
> validation, conformance and performance testing. Without the higher level
> SS7 protocol certification it will be very difficult to find a Telco that
> will let you connect directly to their switches...

As for TE410P/TE405P based on Infineon's PEF22554 QuadFALC chip, there is a partial support for off-load FISU/LSSU
processing/generation from CPU to framer chip. Look, for example, chapters 4.1.14.2 (SS7 receiving) and 4.4.7.2 (SS7
transmitting) for E1 mode at QuadFALC's datasheet.

Also, TE410P/TE405P have Xilinx chip which is used for implementation of a bridge between PCI bus and QuadFALC chip. It
could be possible to move some SS7-related processing from CPU to this chip (may be replacement of Xilinx chip would
required, but it is not so big problem).


WBR,
Paul.