[Asterisk-Dev] TE405P *hardware* question

[Andrew Kohlsmith]

Thanks for the reply.

> As I checked out Xilinx's datasheets CPLD used for TE410P's PCI bridge is
> Spartan II-E family which is maximum 3.3V capable, while regular Spartan-II
> family (which is, I think, used for TE405P) is supports both 3.3 and 5V for
> I/O pins, but requires different termination for each voltage. I don't have
> TE405P, but as I remember there was a sort of problems with some chipsets.
> May be TE410P have ones too but they are not reproducible because "ugly"
> chipset (or motherboard vendors) isn't support 3.3V for this chipset.

http://direct.xilinx.com/bvdocs/publications/ds001_2.pdf

Page 30 says that it can indeed use 3.3V or 5V for PCI, and that the clamps 
need to be different for 5V tolerant systems (which the TE405P is), so that 
much should work...

The next page goes on to say that the standard doesn't require use of Vref of 
board term voltage, only 3.3V on Vcco.  Now it goes on to say that I/O 
configured for PCI 33MHz 5V standard are also 5V tolerant...  we know all 
that since the card is a 5V card.  :-)

Page 43 gives the PCI 3V and 5V buffer Voltage specifications -- it looks like 
there should be no issues whatsoever, I believe that the Vih/il and Voh/ol 
specs are acceptable for both 3V and 5V systems.  Vcco does not change for 5V 
or 3V operation.

The pinout tables are a little confusing for me, but with the information 
gathered so far there shouldn't be any obvious problem with sawing the key 
out for 3V operation.  I would still like to hear from Digium as to whether 
the IOREF is connected to the correct place on the PCI connector, and what 
the unstuffed voltage regulator was to be used for and its part number.

Regards,
Andrew
>
>
> So, I think, the problem is different termination of I/O blocks at the
> Xilinx for 3.3 and 5 V for Spartan-II family.
>
>
> WBR,
> Paul.
>
>
> ----- Original Message -----
> From: "Andrew Kohlsmith" <akohlsmith-asterisk at benshaw.com>
> To: <asterisk-dev at lists.digium.com>
> Sent: Tuesday, April 13, 2004 11:24 PM
> Subject: [Asterisk-Dev] TE405P *hardware* question
>
> > Is there a specific design issue with making the TE405P a universal
> > 3.3V/5V product?  I've done a cursory review of the Xilinx part and it
> > seems that it should be just fine to plug in to a 3V or 5V PCI slot, if I
> > take a hacksaw and create the appropriate key.
> >
> > I haven't yet traced out the VIO pins to make sure that the Spartan will
> > honour the PCI bus voltage.
> >
> > Yes I am almost willing to sacrifice a $1500 card at this point in time. 
> > :-)
> >
> > Can anyone who is familliar with the hardware design of this product
> > explain why there are separate 3V and 5V cards?  Hell even the X101P and
> > TDM400P are dual-voltage capable, what is preventing it on the quad T1/E1
> > cards?
> >
> > Regards,
> > Andrew
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