[dahdi-commits] rmeyerriecks: branch linux/mspiceland/dahdi-qfalc31 r7405 - /linux/team/mspic...

[SVN commits to the DAHDI project]

Author: rmeyerriecks
Date: Thu Oct 15 10:31:41 2009
New Revision: 7405

URL: http://svnview.digium.com/svn/dahdi?view=rev&rev=7405
Log:
Changed the initialization value for Clock Mode Reg 1
1) We don't use TCLK in the design, the only xmit clock
to be referenced is SCLK.
2) We should disable Clock-Switching, as SYNC is also
not to be used as a timing source.

Modified:
    linux/team/mspiceland/dahdi-qfalc31/drivers/dahdi/wct4xxp/base.c

Modified: linux/team/mspiceland/dahdi-qfalc31/drivers/dahdi/wct4xxp/base.c
URL: http://svnview.digium.com/svn/dahdi/linux/team/mspiceland/dahdi-qfalc31/drivers/dahdi/wct4xxp/base.c?view=diff&rev=7405&r1=7404&r2=7405
==============================================================================
--- linux/team/mspiceland/dahdi-qfalc31/drivers/dahdi/wct4xxp/base.c (original)
+++ linux/team/mspiceland/dahdi-qfalc31/drivers/dahdi/wct4xxp/base.c Thu Oct 15 10:31:41 2009
@@ -1769,7 +1769,7 @@
 	unsigned int timing;
 	int x;
 	if (unit != wc->syncsrc) {
-		timing = 0x34;		/* CMR1: RCLK unit, 8.192 Mhz TCLK, RCLK is 8.192 Mhz */
+		timing = 0x38;		/* CMR1: RCLK unit, 8.192 Mhz TCLK, RCLK is 8.192 Mhz */
 		if ((unit > -1) && (unit < 4)) {
 			timing |= (unit << 6);
 			for (x=0;x<wc->numspans;x++)  /* set all 4 receive reference clocks to unit */