[Asterisk-Dev] More Zaptel/BRI questions

[janvb at caselaboratories.com]

James Harper wrote:

>Continuing on from my barrage of questions yesterday...
>
>The netjet BRI card appears to contain the Tiget320 PCI interface
>controller, which is in turn connected to a Siemens ISAC-S chip, which
>does the frame encoding and decoding.
>
>My understanding of ISDN is that data is transmitted in frames of 16
>data bits (B1) + 16 data bits (B2) + 4 data bits (D) + some
>synchronisation. 4000 of these frames are received per second, which
>gives us the 16 * 4000 = 64kbps rate for the B channels and 4 * 4000 =
>16kbps rate for the D channel. To get the zaptel timing of 1000
>interrupts/second, the card needs to be able to generate an interrupt
>off (at least) every 4th frame. If the best it could do was to generate
>an interrupt per frame, how much would that kill the system in interrupt
>servicing?
>  
>
We (europeans) use the term 2B+D for BRI and 30B+D for PRI  but be aware 
that there are a difference between European and American versions here 
as well. I don't know the US version but tend to remember that they use 
56kbps B channels etc.

The D channels is the same D channel as on PRI with the exception of the 
difference in speed(16 versus 64kbps), Q.921 are not that much different 
from BRI to PRI, but you will find that there are differences in Q.931. 
The current libpri will support some, but not all BRI signalling 
operation's.

Just be aware of variances in the protocols.

As for interrupt's on a Pentium, the less the better. The actual penalty 
depends very much on which Pentium you use, but I would avoid a need for 
an interrupt 8000 times a second etc.

>Can anyone tell me what sort of pre-processing needs to be done to the
>raw data from a [BP]RI card into the zaptel driver? I assume that the D
>channel needs to be decoded from the raw bits on the line (or does
>it...?), but does the zaptel logic need anything more than raw bits from
>the B channels? 
>
Only for the D channels, but you should get the D channel from the FIFO 
on the ISAC.

>I'm not really familiar with PRI cards, but in the BRI
>space there are 'passive' cards, 'semi-active' card, and 'active'
>cards... can zaptel cope with different levels of processing being done
>on the card, or does it like to do it all itself? Or none of it itself?
>  
>
The D channel should be supported with a HDLC framer in the ISAC and I 
assume there is a special FIFO for the HDLC you need to service. Beware 
that you need to run the LAPD variant, but there are samples on how to 
config the chip for this on Infeneon's site.

You probably need to make a special zaotel based driver for each card in 
the same way as there is a driver for TE110P etc. It is only your 
interface that need's to be zaptel (I think) for this driver to go 
straight into Asterisk.

>I've had a look around for this sort of documentation, and it doesn't
>appear to exist except in the code, which is fine, it will just take me
>a bit longer :)
>  
>
Actually, it is not that complicated.

You will probably find that the ISAC ship is available on the PCI with 
all it's registers through the Tiger320 etc, so you can write a few 
wrapper functions to set/read registers and it's the standard ISAC doc 
from there. Have a look into the source of TE110P, this uses the 
Tiger320 with a Falc56 so it's not that much different from what you 
need to do to have an ISAC w/Tiger320 etc. I have no glue about the 
netjet card's thought.

Jan