[svn-commits] tzafrir: linux/trunk r8872 - /linux/trunk/drivers/dahdi/xpp/init_card_4_30

[SVN commits to the Digium repositories]

Author: tzafrir
Date: Tue Jul 13 02:22:02 2010
New Revision: 8872

URL: http://svnview.digium.com/svn/dahdi?view=rev&rev=8872
Log:
partial fix of T1 returning signaling register in non-CAS mode

Modified:
    linux/trunk/drivers/dahdi/xpp/init_card_4_30

Modified: linux/trunk/drivers/dahdi/xpp/init_card_4_30
URL: http://svnview.digium.com/svn/dahdi/linux/trunk/drivers/dahdi/xpp/init_card_4_30?view=diff&rev=8872&r1=8871&r2=8872
==============================================================================
--- linux/trunk/drivers/dahdi/xpp/init_card_4_30 (original)
+++ linux/trunk/drivers/dahdi/xpp/init_card_4_30 Tue Jul 13 02:22:02 2010
@@ -238,6 +238,7 @@
 sub port_setup($) {
 	my $port = shift;
 	my $portno = $port->{PORT_NUM};
+	my $pri_protocol = $port->get_pri_protocol;
 
 	my $cmr5 = sprintf("%x", ($portno << 5));
 
@@ -302,10 +303,13 @@
 	PRI::gen "$portno WD 3F $sic2";	# SIC2: No FFS, no center receive elastic buffer, data active at phase ($sic >> 1)
 		
 	# enable the following interrupt sources
+	PRI::gen "$portno WD 14 F7"; 	# IMR0 (Interrupt Mask Register2): Enable CASC_E1/RSC_T1
 	PRI::gen "$portno WD 16 00"; 	# IMR2 (Interrupt Mask Register2): Enable ALL
 		
 	PRI::gen "$portno WD 17 3F"; 	# IMR3 ~ES, ~SEC (Enable ES and SEC interrupts)
 	PRI::gen "$portno WD 18 00"; 	# IMR4: Enable ALL
+	PRI::gen "$portno WD 46 80"; 	# GCR: (Global Configuration Register)
+					#      VIS (Masked Interrupts Visible)
 
 	PRI::gen "$portno WD 08 04";	# IPC: SYNC is 8 Khz
 
@@ -334,9 +338,14 @@
 					#      MDS  (Mode Select) = 100 (No address comparison)
 					#      HRAC (Receiver Active - HDLC channel 1) 
 					#      RFT2 (HDLC Receive FIFO is 64 byte deep)
-	PRI::gen "$portno WD 09 18";	# CCR1 (Common Configuration Register1)
+	my $ccr1 = 0x18;		# CCR1 (Common Configuration Register1)
 					#      EITS (Enable Internal Time Slot 0 to 31 Signalling)
 					#      ITF  (Interframe Time Fill)
+	if ( $pri_protocol eq 'T1' ) {
+		$ccr1 |= 0x80;		#      RSCC (Serial CAS Format Selection)
+	}
+
+	PRI::gen "$portno WD 09 %02X", $ccr1;
 	PRI::gen "$portno WD 0A 04";	# CCR2 (Common Configuration Register2)
 					#      RCRC (enable CRC - HDLC channel 1enable CRC - HDLC channel 1)
 	PRI::gen "$portno WD 0C 00";	# RTR1 (Receive  Time Slot register 1)