[svn-commits] rmeyerriecks: branch linux/mspiceland/dahdi-qfalc31 r7412 - /linux/team/mspic...
SVN commits to the Digium repositories
svn-commits at lists.digium.com
Fri Oct 23 14:41:47 CDT 2009
Author: rmeyerriecks
Date: Fri Oct 23 14:41:44 2009
New Revision: 7412
URL: http://svnview.digium.com/svn/dahdi?view=rev&rev=7412
Log:
Reworked the timing code so it makes more logical sense. Both the SCLK and RCLK
timing sources are explicitly defined. This allows for a valid RCLK DCO source
regardless of SCLK's source. This fixes the broken multiplexer problem on
the 3.1 chip and is backwards compatible with the 2.1 chips.
Modified:
linux/team/mspiceland/dahdi-qfalc31/drivers/dahdi/wct4xxp/base.c
Modified: linux/team/mspiceland/dahdi-qfalc31/drivers/dahdi/wct4xxp/base.c
URL: http://svnview.digium.com/svn/dahdi/linux/team/mspiceland/dahdi-qfalc31/drivers/dahdi/wct4xxp/base.c?view=diff&rev=7412&r1=7411&r2=7412
==============================================================================
--- linux/team/mspiceland/dahdi-qfalc31/drivers/dahdi/wct4xxp/base.c (original)
+++ linux/team/mspiceland/dahdi-qfalc31/drivers/dahdi/wct4xxp/base.c Fri Oct 23 14:41:44 2009
@@ -391,6 +391,8 @@
static void t4_tsi_assign(struct t4 *wc, int fromspan, int fromchan, int tospan, int tochan);
static void t4_tsi_unassign(struct t4 *wc, int tospan, int tochan);
static void __t4_set_timing_source(struct t4 *wc, int unit, int master, int slave);
+static void __t4_set_rclk_src(struct t4 *wc, int span);
+static void __t4_set_sclk_src(struct t4 *wc, int mode, int master, int slave);
static void t4_check_alarms(struct t4 *wc, int span);
static void t4_check_sigbits(struct t4 *wc, int span);
@@ -418,6 +420,9 @@
#define WC_RED (1)
#define WC_GREEN (2)
#define WC_YELLOW (3)
+
+#define WC_RECOVER 0
+#define WC_SELF 1
#define MAX_T4_CARDS 64
@@ -1489,7 +1494,7 @@
printk(KERN_INFO "About to enter spanconfig!\n");
if (debug & DEBUG_MAIN)
- printk(KERN_DEBUG "TE%dXXP: Configuring span %d\n", wc->numspans, span->spanno);
+ printk(KERN_DEBUG "TE%dXXP: Configuring span %d sync %d\n", wc->numspans, span->spanno, lc->sync);
if (lc->sync < 0)
lc->sync = 0;
@@ -1764,6 +1769,45 @@
static spinlock_t synclock = SPIN_LOCK_UNLOCKED;
#endif
+static void __t4_set_rclk_src(struct t4 *wc, int span)
+{
+ int cmr1 = 0x38; /* Clock Mode: RCLK sourced by DCO-R1
+ by default, Disable Clock-Switching */
+
+ if(span != wc->syncsrc) {
+ if (debug & DEBUG_MAIN)
+ printk(KERN_DEBUG "TE%dXXP: RCLK source already set to\
+ span %d\n", wc->numspans, span+1);
+ }
+
+ cmr1 |= (span << 6);
+ __t4_framer_out(wc, 0, 0x44, cmr1);
+
+ if(debug & DEBUG_MAIN)
+ printk(KERN_DEBUG "TE%dXXP: RCLK source set to\
+ span %d\n", wc->numspans, span+1);
+}
+
+static void __t4_set_sclk_src(struct t4 *wc, int mode, int master, int slave)
+{
+ if (slave)
+ wc->dmactrl |= (1 << 25);
+ else
+ wc->dmactrl &= ~(1 << 25);
+ if (master)
+ wc->dmactrl |= (1 << 24);
+ else
+ wc->dmactrl &= ~(1 << 24);
+
+ if(mode == WC_RECOVER)
+ wc->dmactrl |= (1 << 29); /* Recover timing from RCLK */
+
+ if(mode == WC_SELF)
+ wc->dmactrl &= ~(1 << 29);/* Provide timing from MCLK */
+
+ __t4_pci_out(wc, WC_DMACTRL, wc->dmactrl);
+}
+
static void __t4_set_timing_source(struct t4 *wc, int unit, int master, int slave)
{
unsigned int timing;
@@ -1772,13 +1816,19 @@
timing = 0x38; /* Clock Mode: RCLK sourced by DCO-R1
by default, Disable Clock-Switching */
if ((unit > -1) && (unit < 4)) {
+ /* We must have a valid RCLK, so dynamically select
+ an RCLK based on available non-los spans */
timing |= (unit << 6);
- for (x=0;x<wc->numspans;x++) /* set all 4 receive reference clocks to unit */
- __t4_framer_out(wc, x, 0x44, timing);
+ __t4_framer_out(wc, 0, 0x44, timing | (x<<6));
+
+ /* Select RCLK for SCLK */
wc->dmactrl |= (1 << 29);
} else {
- for (x=0;x<wc->numspans;x++) /* set each receive reference clock to itself */
- __t4_framer_out(wc, x, 0x44, timing | (x << 6));
+ /* We must have a valid RCLK, so dynamically select
+ an RCLK based on available non-los spans */
+ __t4_framer_out(wc, 0, 0x44, timing | (x<<6));
+
+ /* Select MCLK for SCLK */
wc->dmactrl &= ~(1 << 29);
}
if (slave)
@@ -1890,22 +1940,63 @@
static void __t4_set_timing_source_auto(struct t4 *wc)
{
int x;
+ int firstprio, secondprio;
+ firstprio = secondprio = 4;
+
printk(KERN_INFO "timing source auto card %d!\n", wc->num);
clear_bit(T4_CHECK_TIMING, &wc->checkflag);
if (timingcable) {
__t4_findsync(wc);
} else {
+ printk(KERN_DEBUG "Evaluating spans for timing sources:\n");
for (x=0;x<wc->numspans;x++) {
- if (wc->tspans[x]->sync) {
- if ((wc->tspans[wc->tspans[x]->psync - 1]->span.flags & DAHDI_FLAG_RUNNING) &&
- !(wc->tspans[wc->tspans[x]->psync - 1]->span.alarms & (DAHDI_ALARM_RED | DAHDI_ALARM_BLUE) )) {
- /* Valid timing source */
- __t4_set_timing_source(wc, wc->tspans[x]->psync - 1, 0, 0);
+ if ((wc->tspans[x]->span.flags & DAHDI_FLAG_RUNNING) &&
+ !(wc->tspans[x]->span.alarms & (DAHDI_ALARM_RED | DAHDI_ALARM_BLUE) )) {
+ printk(KERN_DEBUG "span %d is green : syncpos %d\n", x+1, wc->tspans[x]->syncpos);
+ if(wc->tspans[x]->syncpos){
+ /* If our current timing source is in
+ this list, stay locked to it */
+ if(x == wc->syncsrc){
+ printk(KERN_DEBUG "RCLK syncsrc: %d== offset: %d?\n", wc->syncsrc, x);
return;
+ }
+ /* Valid rsync source in recovered timing mode */
+ if(firstprio == 4)
+ firstprio = x;
+ else if(wc->tspans[x]->syncpos > wc->tspans[firstprio]->syncpos)
+ firstprio = x;
+ }else {
+ /* Valid rsync source in system timing mode */
+ if(secondprio == 4)
+ secondprio = x;
+ else if(wc->tspans[x]->syncpos > wc->tspans[secondprio]->syncpos)
+ secondprio = x;
+
}
}
}
- __t4_set_timing_source(wc, 4, 0, 0);
+ printk(KERN_DEBUG "firstprio %d : secondprio %d\n",
+ firstprio, secondprio);
+ if(firstprio != 4) {
+ wc->syncsrc = firstprio;
+ __t4_set_rclk_src(wc, firstprio);
+ __t4_set_sclk_src(wc, WC_RECOVER, 0, 0);
+ printk(KERN_INFO "Recovered timing mode, RCLK set to\
+ span %d\n", firstprio+1);
+ } else if(secondprio != 4) {
+ wc->syncsrc = -1;
+ __t4_set_rclk_src(wc, secondprio);
+ __t4_set_sclk_src(wc, WC_SELF, 0, 0);
+ printk(KERN_INFO "System timing mode, RCLK set to span\
+ %d\n", secondprio+1);
+ } else {
+ wc->syncsrc = -1;
+ printk(KERN_INFO "All spans in alarm : No valid span to\
+ source RCLK from\n");
+ /* Default rclk to lock with span 1 */
+ __t4_set_rclk_src(wc, 0);
+ __t4_set_sclk_src(wc, WC_SELF, 0, 0);
+ }
}
}
@@ -2116,7 +2207,7 @@
}
#endif
/* Force re-evaluation fo timing source */
- if (timingcable)
+// if (timingcable)
wc->syncsrc = -1;
if (ts->spantype == TYPE_E1) { /* if this is an E1 card */
@@ -2573,10 +2664,12 @@
}
if (c & 0xa0) {
- if (ts->alarmcount >= alarmdebounce)
+ if (ts->alarmcount >= alarmdebounce){
+ printk(KERN_INFO "Loss of Signal card %d span %d\n", wc->num, span+1);
alarms |= DAHDI_ALARM_RED;
- else
+ }else{
ts->alarmcount++;
+ }
} else
ts->alarmcount = 0;
if (c & 0x40)
@@ -2988,7 +3081,7 @@
/* Acknowledge any pending interrupts */
t4_pci_out(wc, WC_INTR, 0x00000000);
spin_lock(&wc->reglock);
- __t4_set_timing_source(wc, 4, 0, 0);
+ __t4_set_sclk_src(wc, WC_SELF, 0, 0);
spin_unlock(&wc->reglock);
return IRQ_RETVAL(1);
}
@@ -3602,7 +3695,7 @@
}
set_bit(T4_CHECK_TIMING, &wc->checkflag);
spin_lock_irqsave(&wc->reglock, flags);
- __t4_set_timing_source(wc,4, 0, 0);
+ __t4_set_sclk_src(wc, WC_SELF, 0, 0);
spin_unlock_irqrestore(&wc->reglock, flags);
tasklet_init(&wc->t4_tlet, t4_isr_bh, (unsigned long)wc);
return 0;
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