[Asterisk-cvs] zaptel pciradio.rbt, NONE, 1.1 pciradio.ucf, NONE,
1.1 pciradio.vhd, NONE, 1.1 Makefile, 1.55, 1.56 pciradio.c,
1.2, 1.3
jim at lists.digium.com
jim at lists.digium.com
Sat Nov 20 23:29:58 CST 2004
Update of /usr/cvsroot/zaptel
In directory mongoose.digium.com:/tmp/cvs-serv13828
Modified Files:
Makefile pciradio.c
Added Files:
pciradio.rbt pciradio.ucf pciradio.vhd
Log Message:
Added support files for new version of pciradio card and updates to driver.
--- NEW FILE: pciradio.rbt ---
Xilinx ASCII Bitstream
Created by Bitstream E.33
Design name: pciradio.ncd
Architecture: spartan2
Part: 2s30vq100
Date: Sat Nov 20 21:18:41 2004
Bits: 336768
11111111111111111111111111111111
10101010100110010101010101100110
00110000000000001000000000000001
00000000000000000000000000000111
00110000000000010110000000000001
00000000000000000000000000001000
00110000000000010010000000000001
00100000100000000011111100101101
00110000000000001100000000000001
00000000000000000000000000000000
00110000000000001000000000000001
00000000000000000000000000001001
[...10492 lines suppressed...]
00110000000000000100000000001001
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00110000000000001000000000000001
00000000000000000000000000000101
00110000000000001010000000000001
00000000000000000000000000000000
00110000000000000000000000000001
00000000000000001100000101111101
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
--- NEW FILE: pciradio.ucf ---
NET "A<0>" LOC = "P82";
NET "A<1>" LOC = "P83";
NET "A<2>" LOC = "P84";
NET "A<3>" LOC = "P86";
NET "D<0>" LOC = "P73";
NET "D<1>" LOC = "P70";
NET "D<2>" LOC = "P69";
NET "D<3>" LOC = "P66";
NET "D<4>" LOC = "P60";
NET "D<5>" LOC = "P57";
NET "D<6>" LOC = "P56";
NET "D<7>" LOC = "P53";
NET "LED<0>" LOC = "P55" ;
NET "LED<1>" LOC = "P58" ;
NET "LED<2>" LOC = "P59" ;
NET "LED<3>" LOC = "P62" ;
NET "LED<4>" LOC = "P65" ;
NET "LED<5>" LOC = "P67" ;
NET "LED<6>" LOC = "P68" ;
NET "LED<7>" LOC = "P71" ;
NET "CLK0" LOC = "P39" ;
NET "CLK" LOC = "P34" ;
NET "FS<0>" LOC = "P22" ;
NET "FS<1>" LOC = "P30" ;
NET "FS<2>" LOC = "P31" ;
NET "FS<3>" LOC = "P32" ;
NET "READ" LOC = "P88" ;
NET "WRITE" LOC = "P36" ;
NET "TJFSC" LOC = "P93" ;
NET "led<0>" DRIVE = 24;
NET "led<1>" DRIVE = 24;
NET "led<2>" DRIVE = 24;
NET "led<3>" DRIVE = 24;
NET "led<4>" DRIVE = 24;
NET "led<5>" DRIVE = 24;
NET "led<6>" DRIVE = 24;
NET "led<7>" DRIVE = 24;
NET "led<0>" IOSTANDARD = LVTTL;
NET "led<1>" IOSTANDARD = LVTTL;
NET "led<2>" IOSTANDARD = LVTTL;
NET "led<3>" IOSTANDARD = LVTTL;
NET "led<4>" IOSTANDARD = LVTTL;
NET "led<5>" IOSTANDARD = LVTTL;
NET "led<6>" IOSTANDARD = LVTTL;
NET "led<7>" IOSTANDARD = LVTTL;
NET "cor<0>" LOC = "p18";
NET "cor<1>" LOC = "p19";
NET "cor<2>" LOC = "p20";
NET "cor<3>" LOC = "p21";
NET "cs<0>" LOC = "p44";
NET "cs<1>" LOC = "p45";
NET "cs<2>" LOC = "p46";
NET "cs<3>" LOC = "p47";
NET "din" LOC = "p41";
NET "dout" LOC = "p43";
NET "irq" LOC = "p54";
NET "ptt<0>" LOC = "p13";
NET "ptt<1>" LOC = "p15";
NET "ptt<2>" LOC = "p16";
NET "ptt<3>" LOC = "p17";
NET "sclk" LOC = "p40";
NET "test<0>" LOC = "p95";
NET "test<1>" LOC = "p96";
NET "test<2>" LOC = "p97";
NET "test<3>" LOC = "p98";
NET "a<0>" IOSTANDARD = LVTTL;
NET "a<1>" IOSTANDARD = LVTTL;
NET "a<2>" IOSTANDARD = LVTTL;
NET "a<3>" IOSTANDARD = LVTTL;
NET "clk" IOSTANDARD = LVTTL;
NET "clk0" IOSTANDARD = LVTTL;
NET "cor<0>" IOSTANDARD = LVTTL;
NET "cor<1>" IOSTANDARD = LVTTL;
NET "cor<2>" IOSTANDARD = LVTTL;
NET "cor<3>" IOSTANDARD = LVTTL;
NET "cs<0>" IOSTANDARD = LVTTL;
NET "cs<1>" IOSTANDARD = LVTTL;
NET "cs<2>" IOSTANDARD = LVTTL;
NET "cs<3>" IOSTANDARD = LVTTL;
NET "d<0>" IOSTANDARD = LVTTL;
NET "d<1>" IOSTANDARD = LVTTL;
NET "d<2>" IOSTANDARD = LVTTL;
NET "d<3>" IOSTANDARD = LVTTL;
NET "d<4>" IOSTANDARD = LVTTL;
NET "d<5>" IOSTANDARD = LVTTL;
NET "d<6>" IOSTANDARD = LVTTL;
NET "d<7>" IOSTANDARD = LVTTL;
NET "din" IOSTANDARD = LVTTL;
NET "dout" IOSTANDARD = LVTTL;
NET "fs<0>" IOSTANDARD = LVTTL;
NET "fs<1>" IOSTANDARD = LVTTL;
NET "fs<2>" IOSTANDARD = LVTTL;
NET "fs<3>" IOSTANDARD = LVTTL;
NET "irq" IOSTANDARD = LVTTL;
NET "ptt<0>" IOSTANDARD = LVTTL;
NET "ptt<1>" IOSTANDARD = LVTTL;
NET "ptt<2>" IOSTANDARD = LVTTL;
NET "ptt<3>" IOSTANDARD = LVTTL;
NET "read" IOSTANDARD = LVTTL;
NET "sclk" IOSTANDARD = LVTTL;
NET "test<0>" IOSTANDARD = LVTTL;
NET "test<1>" IOSTANDARD = LVTTL;
NET "test<2>" IOSTANDARD = LVTTL;
NET "test<3>" IOSTANDARD = LVTTL;
NET "tjfsc" IOSTANDARD = LVTTL;
NET "write" IOSTANDARD = LVTTL;
NET "ptt<0>" PULLUP;
NET "ptt<1>" PULLUP;
NET "ptt<2>" PULLUP;
NET "ptt<3>" PULLUP;
NET "cor<0>" PULLUP;
NET "cor<1>" PULLUP;
NET "cor<2>" PULLUP;
NET "cor<3>" PULLUP;
--- NEW FILE: pciradio.vhd ---
-- Prototype VHDL for Zapata Telephony PCI Radio Card, Rev. A 11/20/04
-- Author: Jim Dixon, WB6NIL <jim at lambdatel.com>
--
-- Copyright (c) 2001-2002, Jim Dixon.
--
-- Jim Dixon <jim at lambdatel.com>
--
-- This program is free software, and the design, schematics, layout,
-- and artwork for the hardware on which it runs is free, and all are
-- distributed under the terms of the GNU General Public License.
--
-- Implements the following registers:
--
-- Offset 0, Write
-- Bit 0 - SCLK
-- Bit 1 - DIN
-- Bit 4-7 CS0 thru CS3
--
-- Offset 1, Write
-- Bit 0-3 - PTT 0-3
-- Bit 4-7 - Test 0-3
--
-- Offset 2, Write
-- Bit 0-7 - LED's
--
-- Offset 0, Read
-- Bit 0-3 - COR 0-3
-- Bit 4 - DOUT
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pciradio is
Port ( CLK0 : in std_logic;
RST : in std_logic;
CLK : out std_logic;
FS : out std_logic_vector(3 downto 0);
WRITE : in std_logic;
READ : in std_logic;
A : in std_logic_vector(3 downto 0);
D : inout std_logic_vector(7 downto 0);
LED : out std_logic_vector(7 downto 0);
COR : in std_logic_vector(3 downto 0);
PTT : out std_logic_vector(3 downto 0);
TEST : out std_logic_vector(3 downto 0);
CS : out std_logic_vector( 3 downto 0);
SCLK : out std_logic;
DIN : out std_logic;
DOUT : in std_logic;
IRQ : in std_logic;
TJFSC : out std_logic );
end pciradio;
architecture Behavioral of pciradio is
component IBUFG
port
(
I : in std_logic;
O : out std_logic
);
end component;
signal counter: std_logic_vector(8 downto 0);
signal WR,RD : std_logic;
signal DBW,DBR : std_logic_vector(7 downto 0);
begin
ibufg_rd : IBUFG
port map
(
I => READ,
O => RD
);
ibufg_wr : IBUFG
port map
(
I => WRITE,
O => WR
);
CLK <= not counter(0);
doclk: process(CLK0)
begin
if CLK0'event and CLK0='0' then
counter <= counter + 1;
end if;
end process;
makefs: process(counter)
begin
TJFSC <= '0';
if (counter = "00000000") then
TJFSC <= '1';
elsif (counter = "111111110") then
FS <= "0001";
elsif (counter = "000001110")then
FS <= "0010";
elsif (counter = "000011110") then
FS <= "0100";
elsif (counter = "000101110") then
FS <= "1000";
else FS <= "0000";
end if;
end process;
iowrite: process(A,WR)
begin
if(RST = '0') then
TEST <= "0000";
PTT <= "1111";
LED <= "00000000";
CS <= "1111";
DIN <= '0';
SCLK <= '0';
elsif(WR'event) and (WR = '1') then
if(A = "0001") then
TEST <= DBW(7 downto 4);
PTT <= not DBW(3 downto 0);
elsif(A = "0010") then
LED <= DBW;
elsif(A = "0000") then
SCLK <= DBW(0);
DIN <= DBW(1);
CS <= DBW(7 downto 4);
end if;
end if;
end process iowrite;
rdmux : process(A)
begin
if(A = "0000") then
DBR(3 downto 0) <= COR;
DBR(4) <= DOUT;
DBR(5) <= IRQ;
DBR(7 downto 6) <= "00";
else
DBR <= "00000000";
end if;
end process rdmux;
D <= DBR when RD = '0' else "ZZZZZZZZ";
DBW <= D;
end Behavioral;
Index: Makefile
===================================================================
RCS file: /usr/cvsroot/zaptel/Makefile,v
retrieving revision 1.55
retrieving revision 1.56
diff -u -d -r1.55 -r1.56
--- Makefile 6 Nov 2004 16:40:42 -0000 1.55
+++ Makefile 21 Nov 2004 04:29:53 -0000 1.56
@@ -120,7 +120,7 @@
wctdm.o:wctdm.c zaptel.h wctdm.h
$(HOSTCC) $(KFLAGS) -c wctdm.c
-pciradio.o:pciradio.c zaptel.h
+pciradio.o:pciradio.c zaptel.h radfw.h
$(HOSTCC) $(KFLAGS) -c pciradio.c
wcs3200p.o:wcs3200p.c zaptel.h
@@ -155,6 +155,9 @@
tor2fw.h: makefw tormenta2.rbt
./makefw tormenta2.rbt tor2fw > tor2fw.h
+radfw.h: makefw pciradio.rbt
+ ./makefw pciradio.rbt radfw > radfw.h
+
gendigits: gendigits.o
$(CC) -o gendigits gendigits.o -lm
Index: pciradio.c
===================================================================
RCS file: /usr/cvsroot/zaptel/pciradio.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- pciradio.c 5 Nov 2004 02:55:58 -0000 1.2
+++ pciradio.c 21 Nov 2004 04:29:53 -0000 1.3
@@ -67,17 +67,15 @@
#define RAD_OPER 0x01
#define RAD_AUXC 0x02
#define RAD_AUXD 0x03
- #define MX828_DOUT 0x02 /* Data from MX828 */
- #define MX828_DIN 0x04 /* Data to MX828 */
- #define MX828_CS0 0x08 /* MX828 CS Channel 0 */
- #define MX828_CS1 0x10 /* MX828 CS Channel 1 */
- #define MX828_CS2 0x20 /* MX828 CS Channel 2 */
- #define MX828_CS3 0x40 /* MX828 CS Channel 3 */
- #define MX828_SCLK 0x80 /* MX828 Serial Clock */
+ #define XPGM 4
+ #define XCS 2
+
#define RAD_MASK0 0x04
#define RAD_MASK1 0x05
#define RAD_INTSTAT 0x06
#define RAD_AUXR 0x07
+ #define XINIT 8
+ #define XDONE 0x10
#define RAD_DMAWS 0x08
#define RAD_DMAWI 0x0c
@@ -105,6 +103,16 @@
#define RAD_GOTRX_DEBOUNCE_TIME 75
+/* bits for port 0 in */
+#define MX828_DOUT 0x10 /* Data from MX828 */
+/* bits for port 0 out */
+#define MX828_DIN 0x2 /* Data to MX828 */
+#define MX828_CS0 0x10 /* MX828 CS Channel 0 */
+#define MX828_CS1 0x20 /* MX828 CS Channel 1 */
+#define MX828_CS2 0x40 /* MX828 CS Channel 2 */
+#define MX828_CS3 0x80 /* MX828 CS Channel 3 */
+#define MX828_SCLK 0x1 /* MX828 Serial Clock */
+
/*
* MX828 Commands
*/
@@ -185,6 +193,7 @@
unsigned char b2;
} ;
+#include "radfw.h"
static struct tonedef cttable_tx [] = {
{0,0,0},
@@ -448,169 +457,156 @@
}
/*
-* Output a byte to the MX828 ctcss encoder/decoder chip
+* Output a byte to the MX828 PL encoder/decoder chip
*/
-
-void mx828_set_serdata(struct pciradio *rad, char bit)
+
+void mx828_set_serdata(struct pciradio *rad,int bit)
{
- unsigned char regsave;
-
- regsave = inb(rad->ioaddr + RAD_AUXR);
- regsave &= ~MX828_DIN;
- if(bit)
- regsave |= MX828_DIN;
- outb(regsave, rad->ioaddr + RAD_AUXD);
+ rad->p0save &= ~MX828_DIN;
+ if(bit)
+ rad->p0save |= MX828_DIN;
+ __pciradio_setcreg(rad,0,rad->p0save);
}
-
+
void mx828_wiggle_sclk(struct pciradio *rad)
{
- unsigned char regsave;
-
- regsave = inb(rad->ioaddr + RAD_AUXR);
- regsave &= ~MX828_SCLK; /* SCLK 1 -> 0 */
- outb(regsave, rad->ioaddr + RAD_AUXD);
+ rad->p0save &= ~MX828_SCLK; /* SCLK 1 -> 0 */
+ __pciradio_setcreg(rad,0,rad->p0save);
udelay(1);
-
- regsave = inb(rad->ioaddr + RAD_AUXR);
- regsave |= MX828_SCLK; /* SCLK 0 -> 1 */
- outb(regsave, rad->ioaddr + RAD_AUXD);
+ rad->p0save |= MX828_SCLK; /* SCLK 0 -> 1 */
+ __pciradio_setcreg(rad,0,rad->p0save);
udelay(1);
}
-
-
+
+
/*
* Output a command to the MX828 over the serial bus
*/
-
-
+
+
void mx828_command(struct pciradio *rad,int channel, unsigned char command, unsigned char *byte1, unsigned char *byte2)
{
-
- int i, param = 1, wr = 1, word = 0;
- unsigned char byte, regsave;
-
- if(channel > 3)
- return;
-
- /* Pull the transfer info from the command code */
-
- switch(command){
- case MX828_GEN_RESET: /* Commands with no param */
- param = 0;
- break;
-
- case MX828_SAUDIO_CTRL: /* 8 bit write commands */
- case MX828_SAUDIO_SETUP:
- case MX828_DCS1:
- case MX828_DCS2:
- case MX828_DCS3:
- case MX828_IRQ_MASK:
- case MX828_GEN_CTRL:
- case MX828_GPT:
- break;
-
- case MX828_SAUDIO_STATUS: /* 8 bit read commands */
- case MX828_IRQ_FLAG:
- case 0:
- wr = 0;
- break;
-
- case MX828_TX_TONE: /* 16 bit write commands */
- case MX828_RX_TONE:
- case MX828_AUD_CTRL:
- case MX828_SELCALL:
- word = 1;
- break;
-
- default:
- return;
- }
-
-
- mx828_set_serdata(rad,1); /* Start with data = 1 */
-
+
+ int i, param = 1, wr = 1, word = 0;
+ unsigned char byte;
+
+ if(channel > 3)
+ return;
+
+ /* Pull the transfer info from the command code */
+
+ switch(command){
+ case MX828_GEN_RESET: /* Commands with no param */
+ param = 0;
+ break;
+
+ case MX828_SAUDIO_CTRL: /* 8 bit write commands */
+ case MX828_SAUDIO_SETUP:
+ case MX828_DCS1:
+ case MX828_DCS2:
+ case MX828_DCS3:
+ case MX828_IRQ_MASK:
+ case MX828_GEN_CTRL:
+ case MX828_GPT:
+ break;
+
+ case MX828_SAUDIO_STATUS: /* 8 bit read commands */
+ case MX828_IRQ_FLAG:
+ case 0:
+ wr = 0;
+ break;
+
+ case MX828_TX_TONE: /* 16 bit write commands */
+ case MX828_RX_TONE:
+ case MX828_AUD_CTRL:
+ case MX828_SELCALL:
+ word = 1;
+ break;
+
+ default:
+ return;
+ }
+
+
+ mx828_set_serdata(rad,1); /* Start with data = 1 */
+
udelay(2);
-
- /* Set the proper CS */
-
- byte = (unsigned char ) 1 << (channel + 3);
-
- regsave = inb(rad->ioaddr + RAD_AUXR);
- regsave |= (MX828_CS0 | MX828_CS1 | MX828_CS2 | MX828_CS3);
- regsave &= ~byte;
- outb(regsave, rad->ioaddr + RAD_AUXD);
-
-
+
+ /* Set the proper CS */
+
+ byte = (unsigned char ) 1 << (channel + 4);
+
+ rad->p0save |= (MX828_CS0 | MX828_CS1 | MX828_CS2 | MX828_CS3);
+ rad->p0save &= ~byte;
+ __pciradio_setcreg(rad,0,rad->p0save);
+
+
udelay(2);
-
- /* Output the command byte */
-
- byte = command;
-
- for( i = 0 ; i < 8 ; i++){
- udelay(2);
- mx828_set_serdata(rad,0x80 & byte); /* MSB first */
- byte <<= 1;
- mx828_wiggle_sclk(rad);
- }
- if(param){
- udelay(4);
- if(wr){
- byte = *byte1;
- for( i = 0 ; i < 8 ; i++){
- udelay(2);
- mx828_set_serdata(rad,0x80 & byte);
- byte <<= 1;
- mx828_wiggle_sclk(rad);
- }
- if(word){
- udelay(4);
- byte = *byte2;
- for( i = 0 ; i < 8 ; i++){
- udelay(2);
- mx828_set_serdata(rad,0x80 & byte);
- byte <<= 1;
- mx828_wiggle_sclk(rad);
- }
- }
- }
- else { /* rd */
- byte = 0;
- for( i = 0 ; i < 8 ; i++){
- mx828_wiggle_sclk(rad);
- byte <<= 1;
- udelay(2);
- if(inb(rad->ioaddr + RAD_AUXR) & MX828_DOUT)
- byte |= 0x01;
- }
- *byte1 = byte;
- if(word){
- byte = 0;
- udelay(4);
- for( i = 0 ; i < 8 ; i++){
- mx828_wiggle_sclk(rad);
- byte <<= 1;
- udelay(2);
- if(inb(rad->ioaddr + RAD_AUXR) & MX828_DOUT)
- byte |= 0x01;
- }
- *byte2 = byte;
+
+ /* Output the command byte */
+
+ byte = command;
+
+ for( i = 0 ; i < 8 ; i++){
+ udelay(2);
+ mx828_set_serdata(rad,0x80 & byte); /* MSB first */
+ byte <<= 1;
+ mx828_wiggle_sclk(rad);
+ }
+ if(param){
+ udelay(4);
+ if(wr){
+ byte = *byte1;
+ for( i = 0 ; i < 8 ; i++){
+ udelay(2);
+ mx828_set_serdata(rad,0x80 & byte);
+ byte <<= 1;
+ mx828_wiggle_sclk(rad);
+ }
+ if(word){
+ udelay(4);
+ byte = *byte2;
+ for( i = 0 ; i < 8 ; i++){
+ udelay(2);
+ mx828_set_serdata(rad,0x80 & byte);
+ byte <<= 1;
+ mx828_wiggle_sclk(rad);
+ }
+ }
+ }
+ else { /* rd */
+ byte = 0;
+ for( i = 0 ; i < 8 ; i++){
+ mx828_wiggle_sclk(rad);
+ byte <<= 1;
+ udelay(2);
+ if(__pciradio_getcreg(rad,0) & MX828_DOUT)
+ byte |= 0x01;
+ }
+ *byte1 = byte;
+ if(word){
+ byte = 0;
+ udelay(4);
+ for( i = 0 ; i < 8 ; i++){
+ mx828_wiggle_sclk(rad);
+ byte <<= 1;
+ udelay(2);
+ if(__pciradio_getcreg(rad,0) & MX828_DOUT)
+ byte |= 0x01;
+ }
+ *byte2 = byte;
}
-
-
- }
- }
-
+
+ }
+ }
+
udelay(4);
-
- /* Release chip selects */
-
- regsave = inb(rad->ioaddr + RAD_AUXR);
- regsave |= (MX828_CS0 | MX828_CS1 | MX828_CS2 | MX828_CS3);
- outb(regsave, rad->ioaddr + RAD_AUXD);
-
-
-}
+
+ /* Release chip selects */
+ rad->p0save |= (MX828_CS0 | MX828_CS1 | MX828_CS2 | MX828_CS3);
+ __pciradio_setcreg(rad,0,rad->p0save);
+}
+
static void _set_encdec(struct pciradio *rad, int n)
{
@@ -635,7 +631,7 @@
txcode = rad->txcode[n][myindex];
if (txcode & 0x8000) dcstx = 1; else if (txcode) cttx = 1;
if (rad->radmode[n] & RADMODE_NOENCODE) dcstx = cttx = 0;
- if ((!rad->gottx[n]) || rad->bursttimer[n]) dcstx = cttx = 0;
+ if ((!rad->gottx[n]) || rad->bursttimer[n]) dcstx = cttx = 0;
saudio_ctrl = 0;
saudio_setup = 0;
if (dcstx && (!dcsrx)) /* if to transmit DCS */
@@ -1285,19 +1281,19 @@
{
unsigned char byte1,byte2;
int x;
+unsigned long endjif;
/* Signal Reset */
outb(0x01, rad->ioaddr + RAD_CNTL);
/* Reset PCI Interface chip and registers (and serial) */
outb(0x06, rad->ioaddr + RAD_CNTL);
- /* Setup our proper outputs for when we switch for our "serial" port */
- rad->ios = BIT_CS | BIT_SCLK | BIT_SDI;
-
+ /* Setup our proper outputs */
+ rad->ios = 0xfe;
outb(rad->ios, rad->ioaddr + RAD_AUXD);
- /* Set all to outputs except AUX 2, which is an input */
- outb(0xfd, rad->ioaddr + RAD_AUXC);
+ /* Set all to outputs except AUX 3 & 4, which are inputs */
+ outb(0x67, rad->ioaddr + RAD_AUXC);
/* Select alternate function for AUX0 */
outb(0x4, rad->ioaddr + RAD_AUXFUNC);
@@ -1305,6 +1301,75 @@
/* Wait 1/4 of a sec */
wait_just_a_bit(HZ/4);
+ /* attempt to load the Xilinx Chip */
+ /* De-assert CS+Write */
+ rad->ios |= XCS;
+ outb(rad->ios, rad->ioaddr + RAD_AUXD);
+ /* Assert PGM */
+ rad->ios &= ~XPGM;
+ outb(rad->ios, rad->ioaddr + RAD_AUXD);
+ /* wait for INIT and DONE to go low */
+ endjif = jiffies + 10;
+ while (inb(rad->ioaddr + RAD_AUXR) & (XINIT | XDONE) && (jiffies <= endjif));
+ if (endjif < jiffies) {
+ printk("Timeout waiting for INIT and DONE to go low\n");
+ return -1;
+ }
+ if (debug) printk("fwload: Init and done gone to low\n");
+ /* De-assert PGM */
+ rad->ios |= XPGM;
+ outb(rad->ios, rad->ioaddr + RAD_AUXD);
+ /* wait for INIT to go high (clearing done */
+ endjif = jiffies + 10;
+ while (!(inb(rad->ioaddr + RAD_AUXR) & XINIT) && (jiffies <= endjif));
+ if (endjif < jiffies) {
+ printk("Timeout waiting for INIT to go high\n");
+ return -1;
+ }
+ if (debug) printk("fwload: Init went high (clearing done)\nNow loading...\n");
+ /* Assert CS+Write */
+ rad->ios &= ~XCS;
+ outb(rad->ios, rad->ioaddr + RAD_AUXD);
+ for (x = 0; x < sizeof(radfw); x++)
+ {
+ /* write the byte */
+ outb(radfw[x],rad->ioaddr + RAD_REGBASE);
+ /* if DONE signal, we're done, exit */
+ if (inb(rad->ioaddr + RAD_AUXR) & XDONE) break;
+ /* if INIT drops, we're screwed, exit */
+ if (!(inb(rad->ioaddr + RAD_AUXR) & XINIT)) break;
+ }
+ if (debug) printk("fwload: Transferred %d bytes into chip\n",x);
+ /* Wait for FIFO to clear */
+ endjif = jiffies + 2;
+ while (jiffies < endjif); /* wait */
+ printk("Transfered %d bytes into chip\n",x);
+ /* De-assert CS+Write */
+ rad->ios |= XCS;
+ outb(rad->ios, rad->ioaddr + RAD_AUXD);
+ if (debug) printk("fwload: Loading done!\n");
+ /* Wait for FIFO to clear */
+ endjif = jiffies + 2;
+ while (jiffies < endjif); /* wait */
+ if (!(inb(rad->ioaddr + RAD_AUXR) & XINIT))
+ {
+ printk("Drove Init low!! CRC Error!!!\n");
+ return -1;
+ }
+ if (!(inb(rad->ioaddr + RAD_AUXR) & XDONE))
+ {
+ printk("Did not get DONE signal. Short file maybe??\n");
+ return -1;
+ }
+ printk("Xilinx Chip successfully loaded, configured and started!!\n");
+
+
+ rad->p0save = 0xf0;
+ __pciradio_setcreg(rad,0,rad->p0save);
+
+ rad->p1save = 0;
+ __pciradio_setcreg(rad,1,rad->p1save);
+
/* Back to normal, with automatic DMA wrap around */
outb(0x30 | 0x01, rad->ioaddr + RAD_CNTL);
@@ -1346,7 +1411,7 @@
mx828_command(rad,x, MX828_GEN_CTRL, &byte1, &byte2);
}
- udelay(1000);
+
return 0;
}
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