[dahdi-commits] dahdi/linux.git branch "master" updated.
SVN commits to the DAHDI project
dahdi-commits at lists.digium.com
Mon Nov 11 14:39:57 CST 2013
branch "master" has been updated
via 466acea7e028371294849efbafeb7b38334a7fd5 (commit)
via 3134b36d7eebd46d1f2f1f4c7981cdf7f8ee3e73 (commit)
via 4707e19654e8a35bd102fa273057ba7e506affd5 (commit)
via e42548f2c5e867f10da339f4ceb5cf158c265bed (commit)
via abe35059bc6f4ce0dec6079014578f9604bcbcac (commit)
via 348f6ab030c6323bf1a6d72d2d4bd71142341564 (commit)
via 26efcf6902a58a38fa8d0d3371de3b4cf6765d17 (commit)
via a648cef0f6d4552f64bf3cd57561c0dcb0c89fed (commit)
via a5a52dbe94269722d2997350912e5b8cc1090f22 (commit)
via 43ad3eeb659a18c15c7169e7c4d49513e25d745d (commit)
via 706dc43483e5012a5a8266bd646713750c7d52f2 (commit)
via 92f1e46b8fd700528c7da36c3bcd36f9c1c5d8c7 (commit)
via abb09a012de9de25728afc1927e61e94f36c19e4 (commit)
via 7405dd60380011d8fa46b64cd03fe86eb1616d7c (commit)
via 496f81777323d309bd5c32afc2186bdc0055e5be (commit)
via 4a6ecbbdeb770acf3a7a6ae55d9f8c283ad54f22 (commit)
from bd0366287e90c19cc05c0b26e7eb5c04fff07663 (commit)
Summary of changes:
Makefile | 9 +-
drivers/dahdi/Kbuild | 21 +-
drivers/dahdi/dahdi-base.c | 20 +-
drivers/dahdi/firmware/Makefile | 71 +-
drivers/dahdi/oct612x/{Makefile => Kbuild} | 6 +-
drivers/dahdi/oct612x/oct612x-user.c | 181 +
drivers/dahdi/oct612x/oct612x.h | 49 +
drivers/dahdi/wcaxx-base.c | 4576 +++++++++++++++++++++++
drivers/dahdi/wct4xxp/Kbuild | 4 +-
drivers/dahdi/wct4xxp/base.c | 159 +-
drivers/dahdi/wct4xxp/vpm450m.c | 139 +-
drivers/dahdi/wct4xxp/vpm450m.h | 8 +-
drivers/dahdi/wcte13xp-base.c | 2294 +++++-------
drivers/dahdi/wcte43x-base.c | 3629 ++++++++++++++++++
drivers/dahdi/wcxb.c | 919 +++++
drivers/dahdi/wcxb.h | 184 +
drivers/dahdi/wcxb_flash.c | 170 +
drivers/dahdi/{dahdi-version.c => wcxb_flash.h} | 21 +-
drivers/dahdi/wcxb_spi.c | 382 ++
drivers/dahdi/wcxb_spi.h | 116 +
include/dahdi/dahdi_config.h | 3 +-
include/dahdi/kernel.h | 38 +-
22 files changed, 11426 insertions(+), 1573 deletions(-)
copy drivers/dahdi/oct612x/{Makefile => Kbuild} (91%)
create mode 100644 drivers/dahdi/oct612x/oct612x-user.c
create mode 100644 drivers/dahdi/oct612x/oct612x.h
create mode 100644 drivers/dahdi/wcaxx-base.c
create mode 100644 drivers/dahdi/wcte43x-base.c
create mode 100644 drivers/dahdi/wcxb.c
create mode 100644 drivers/dahdi/wcxb.h
create mode 100644 drivers/dahdi/wcxb_flash.c
copy drivers/dahdi/{dahdi-version.c => wcxb_flash.h} (55%)
create mode 100644 drivers/dahdi/wcxb_spi.c
create mode 100644 drivers/dahdi/wcxb_spi.h
- Log -----------------------------------------------------------------
commit 466acea7e028371294849efbafeb7b38334a7fd5
Author: Wendell Thompson <wthompson at digium.com>
Date: Tue Sep 10 15:54:33 2013 -0500
wcte43x: Add driver for TE435/TE235 digital cards.
From: Wendell Thompson <wthompson at digium.com>
These new cards are based on a common architecture with the TE133/TE134 as well
as the new analog cards, A4A/A4B/A8A/A8B.
Signed-off-by: Shaun Ruffell <sruffell at digium.com>
diff --git a/drivers/dahdi/Kbuild b/drivers/dahdi/Kbuild
index 15357d1..ee2cd59 100644
--- a/drivers/dahdi/Kbuild
+++ b/drivers/dahdi/Kbuild
@@ -18,6 +18,15 @@ wcte13xp-objs := wcte13xp-base.o wcxb_spi.o wcxb.o wcxb_flash.o
CFLAGS_wcte13xp-base.o += -I$(src)/oct612x -I$(src)/oct612x/include -I$(src)/oct612x/octdeviceapi -I$(src)/oct612x/octdeviceapi/oct6100api
ifeq ($(HOTPLUG_FIRMWARE),yes)
CFLAGS_wcte13xp-base.o += -DHOTPLUG_FIRMWARE
+endif
+
+obj-$(DAHDI_BUILD_ALL)$(CONFIG_DAHDI_WCTE43X) += wcte43x.o
+
+wcte43x-objs := wcte43x-base.o wcxb_spi.o wcxb.o wcxb_flash.o
+CFLAGS_wcte43x-base.o += -I$(src)/oct612x -I$(src)/oct612x/include -I$(src)/oct612x/octdeviceapi -I$(src)/oct612x/octdeviceapi/oct6100api
+ifeq ($(HOTPLUG_FIRMWARE),yes)
+ CFLAGS_wcte43x-base.o += -DHOTPLUG_FIRMWARE
+endif
obj-$(DAHDI_BUILD_ALL)$(CONFIG_DAHDI_WCAXX) += wcaxx.o
@@ -26,7 +35,6 @@ CFLAGS_wcaxx-base.o += -I$(src)/oct612x/ -I$(src)/oct612x/include -I$(src)/oct61
ifeq ($(HOTPLUG_FIRMWARE),yes)
CFLAGS_wcaxx-base.o += -DHOTPLUG_FIRMWARE
endif
-endif
obj-$(DAHDI_BUILD_ALL)$(CONFIG_DAHDI_WCTDM) += wctdm.o
obj-$(DAHDI_BUILD_ALL)$(CONFIG_DAHDI_VOICEBUS) += voicebus/
diff --git a/drivers/dahdi/firmware/Makefile b/drivers/dahdi/firmware/Makefile
index ce1e09c..3aec364 100644
--- a/drivers/dahdi/firmware/Makefile
+++ b/drivers/dahdi/firmware/Makefile
@@ -33,6 +33,7 @@ VPMOCT032_VERSION:=1.12.0
WCT820_VERSION:=1.76
TE133_VERSION:=6f0017
TE134_VERSION:=6f0017
+TE435_VERSION:=d0017
A8A_VERSION:=1d0017
A8B_VERSION:=1d0017
A4A_VERSION:=a0017
@@ -42,7 +43,7 @@ FIRMWARE_URL:=http://downloads.digium.com/pub/telephony/firmware/releases
ALL_FIRMWARE=FIRMWARE-OCT6114-032 FIRMWARE-OCT6114-064 FIRMWARE-OCT6114-128 FIRMWARE-OCT6114-256
ALL_FIRMWARE+=FIRMWARE-TC400M FIRMWARE-HX8 FIRMWARE-VPMOCT032 FIRMWARE-TE820 FIRMWARE-TE133 FIRMWARE-TE134
-ALL_FIRMWARE+=FIRMWARE-A8A FIRMWARE-A8B FIRMWARE-A4A FIRMWARE-A4B
+ALL_FIRMWARE+=FIRMWARE-A8A FIRMWARE-A8B FIRMWARE-A4A FIRMWARE-A4B FIRMWARE-TE435
# Firmware files should use the naming convention: dahdi-fw-<base name>-<sub name>-<version> or dahdi-fw-<base name>-<version>
# First example: dahdi-fw-oct6114-064-1.05.01
@@ -61,6 +62,7 @@ FIRMWARE:=$(FIRMWARE:FIRMWARE-VPMOCT032=dahdi-fw-vpmoct032-$(VPMOCT032_VERSION).
FIRMWARE:=$(FIRMWARE:FIRMWARE-TE820=dahdi-fw-te820-$(WCT820_VERSION).tar.gz)
FIRMWARE:=$(FIRMWARE:FIRMWARE-TE133=dahdi-fw-te133-$(TE133_VERSION).tar.gz)
FIRMWARE:=$(FIRMWARE:FIRMWARE-TE134=dahdi-fw-te134-$(TE134_VERSION).tar.gz)
+FIRMWARE:=$(FIRMWARE:FIRMWARE-TE435=dahdi-fw-te435-$(TE435_VERSION).tar.gz)
FIRMWARE:=$(FIRMWARE:FIRMWARE-A8A=dahdi-fw-a8b-$(A8B_VERSION).tar.gz)
FIRMWARE:=$(FIRMWARE:FIRMWARE-A8B=dahdi-fw-a8a-$(A8A_VERSION).tar.gz)
FIRMWARE:=$(FIRMWARE:FIRMWARE-A4A=dahdi-fw-a4b-$(A4B_VERSION).tar.gz)
@@ -235,6 +237,17 @@ ifeq ($(shell if ( [ -f $(DESTDIR)/usr/lib/hotplug/firmware/.dahdi-fw-te134-$(TE
else
@echo "Firmware dahdi-fw-te134.bin is already installed with required version $(TE134_VERSION)"
endif
+ifeq ($(shell if ( [ -f $(DESTDIR)/usr/lib/hotplug/firmware/.dahdi-fw-te435-$(TE435_VERSION) ] ) && ( [ -f $(DESTDIR)/lib/firmware/.dahdi-fw-te435-$(TE435_VERSION) ] ); then echo "no"; else echo "yes"; fi),yes)
+ @echo "Installing dahdi-fw-te435.bin to hotplug firmware directories"
+ @install -m 644 dahdi-fw-te435.bin $(DESTDIR)/usr/lib/hotplug/firmware
+ @rm -rf $(DESTDIR)/usr/lib/hotplug/firmware/.dahdi-fw-te435-*
+ @touch $(DESTDIR)/usr/lib/hotplug/firmware/.dahdi-fw-te435-$(TE435_VERSION)
+ @install -m 644 dahdi-fw-te435.bin $(DESTDIR)/lib/firmware
+ @rm -rf $(DESTDIR)/lib/firmware/.dahdi-fw-te435-*
+ @touch $(DESTDIR)/lib/firmware/.dahdi-fw-te435-$(TE435_VERSION)
+else
+ @echo "Firmware dahdi-fw-te435.bin is already installed with required version $(TE435_VERSION)"
+endif
ifeq ($(shell if ( [ -f $(DESTDIR)/usr/lib/hotplug/firmware/.dahdi-fw-a8a-$(A8A_VERSION) ] ) && ( [ -f $(DESTDIR)/lib/firmware/.dahdi-fw-a8a-$(A8A_VERSION) ] ); then echo "no"; else echo "yes"; fi),yes)
@echo "Installing dahdi-fw-a8a.bin to hotplug firmware directories"
@install -m 644 dahdi-fw-a8a.bin $(DESTDIR)/usr/lib/hotplug/firmware
diff --git a/drivers/dahdi/wcte43x-base.c b/drivers/dahdi/wcte43x-base.c
new file mode 100644
index 0000000..efe1378
--- /dev/null
+++ b/drivers/dahdi/wcte43x-base.c
@@ -0,0 +1,3629 @@
+/*
+ * Digium, Inc. Wildcard te43x T1/E1 card Driver
+ *
+ * Written by Russ Meyerriecks <rmeyerriecks at digium.com>
+ * Copyright (C) 2012 - 2013, Digium, Inc.
+ * All rights reserved.
+ *
+ */
+
+/*
+ * See http://www.asterisk.org for more information about
+ * the Asterisk project. Please do not directly contact
+ * any of the maintainers of this project for assistance;
+ * the project provides a web site, mailing lists and IRC
+ * channels for your use.
+ *
+ * This program is free software, distributed under the terms of
+ * the GNU General Public License Version 2 as published by the
+ * Free Software Foundation. See the LICENSE file included with
+ * this program for more details.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/proc_fs.h>
+#include <linux/moduleparam.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/crc32.h>
+
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/string.h>
+#include <linux/time.h>
+#include <linux/version.h>
+#include <linux/firmware.h>
+#include <oct612x.h>
+
+#include <stdbool.h>
+#include <dahdi/kernel.h>
+
+#include "wct4xxp/wct4xxp.h" /* For certain definitions */
+#include "wcxb.h"
+#include "wcxb_spi.h"
+#include "wcxb_flash.h"
+
+static const char *TE435_FW_FILENAME = "dahdi-fw-te435.bin";
+static const u32 TE435_VERSION = 0xd0017;
+
+/* #define RPC_RCLK */
+#define VPM_SUPPORT
+
+enum linemode {
+ T1 = 1,
+ E1,
+ J1,
+};
+
+#define STATUS_LED_GREEN (1 << 9)
+#define STATUS_LED_RED (1 << 10)
+#define STATUS_LED_YELLOW (STATUS_LED_RED | STATUS_LED_GREEN)
+#define LED_MASK 0x7f8
+#define FALC_CPU_RESET (1 << 11)
+
+/* Interrupt definitions */
+#define FALC_INT (1<<3)
+#define SPI_INT (1<<4)
+#define DMA_STOPPED (1<<5)
+
+struct t43x;
+
+struct t43x_span {
+ struct t43x *owner;
+ struct dahdi_span span;
+ struct {
+ unsigned int nmf:1;
+ unsigned int sendingyellow:1;
+ } flags;
+ unsigned char txsigs[16]; /* Copy of tx sig registers */
+ unsigned long lofalarmtimer;
+ unsigned long losalarmtimer;
+ unsigned long aisalarmtimer;
+ unsigned long yelalarmtimer;
+ unsigned long recoverytimer;
+ unsigned long loopuptimer;
+ unsigned long loopdntimer;
+
+ struct dahdi_chan *chans[32]; /* Channels */
+ struct dahdi_echocan_state *ec[32]; /* Echocan state for channels */
+
+ bool debounce;
+ int syncpos;
+ int sync;
+};
+
+struct t43x_clksrc_work {
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 20)
+ struct work_struct work;
+#else
+ struct delayed_work work;
+#endif
+ spinlock_t lock;
+ enum wcxb_clock_sources clksrc;
+ bool is_timing_master;
+};
+
+/* One structure per card */
+struct t43x {
+ spinlock_t reglock;
+
+ const struct t43x_desc *devtype;
+ unsigned long blinktimer;
+ bool blink;
+ struct dahdi_device *ddev;
+ struct t43x_span *tspans[4];
+ int numspans; /* Number of spans on the card */
+ int spansstarted; /* Number of spans started */
+
+ /* protected by t1.reglock */
+ struct timer_list timer;
+ struct work_struct timer_work;
+ struct workqueue_struct *wq;
+ struct t43x_clksrc_work clksrc_work;
+ unsigned int not_ready; /* 0 when entire card is ready to go */
+#ifdef VPM_SUPPORT
+ struct vpm450m *vpm;
+ char *vpm_name;
+#endif
+ struct mutex lock;
+ bool latency_locked;
+ int syncsrc;
+ int num; /* card index */
+ int intr_span; /* span to service next interrupt */
+
+ struct wcxb xb;
+ struct list_head card_node;
+};
+
+static void t43x_handle_transmit(struct wcxb *xb, void *vfp);
+static void t43x_handle_receive(struct wcxb *xb, void *vfp);
+static void t43x_handle_interrupt(struct wcxb *xb, u32 pending);
+
+static struct wcxb_operations xb_ops = {
+ .handle_receive = t43x_handle_receive,
+ .handle_transmit = t43x_handle_transmit,
+ .handle_interrupt = t43x_handle_interrupt,
+};
+
+/* Maintenance Mode Registers */
+#define LIM0 0x36
+#define LIM0_LL (1<<1)
+#define LIM1 0x37
+#define LIM1_RL (1<<1)
+#define LIM1_JATT (1<<2)
+
+/* Clear Channel Registers */
+#define CCB1 0x2f
+#define CCB2 0x30
+#define CCB3 0x31
+
+#define FECL_T 0x50 /* Framing Error Counter Lower Byte */
+#define FECH_T 0x51 /* Framing Error Counter Higher Byte */
+#define CVCL_T 0x52 /* Code Violation Counter Lower Byte */
+#define CVCH_T 0x53 /* Code Violation Counter Higher Byte */
+#define CEC1L_T 0x54 /* CRC Error Counter 1 Lower Byte */
+#define CEC1H_T 0x55 /* CRC Error Counter 1 Higher Byte */
+#define EBCL_T 0x56 /* E-Bit Error Counter Lower Byte */
+#define EBCH_T 0x57 /* E-Bit Error Counter Higher Byte */
+#define BECL_T 0x58 /* Bit Error Counter Lower Byte */
+#define BECH_T 0x59 /* Bit Error Counter Higher Byte */
+#define COEC_T 0x5A /* COFA Event Counter */
+#define PRBSSTA_T 0xDA /* PRBS Status Register */
+#define FRS1_T 0x4D /* Framer Receive Status Reg 1 */
+
+#define ISR3_SEC (1 << 6) /* Internal one-second interrupt bit mask */
+#define ISR3_ES (1 << 7) /* Errored Second interrupt bit mask */
+
+#define IMR0 0x14
+
+/* pci memory map offsets */
+#define DMA1 0x00 /* dma addresses */
+#define DMA2 0x04
+#define DMA3 0x08
+#define CNTL 0x0C /* fpga control register */
+#define INT_MASK 0x10 /* interrupt vectors from oct and framer */
+#define INT_STAT 0x14
+#define FRAMER_BASE 0x00000800 /* framer's address space */
+
+#define NOSYNC_ALARMS (DAHDI_ALARM_RED | DAHDI_ALARM_BLUE | \
+ DAHDI_ALARM_LOOPBACK)
+
+static int debug;
+static int timingcable;
+static int force_firmware;
+static int alarmdebounce = 2500; /* LOF/LFA def to 2.5s AT&T TR54016*/
+static int losalarmdebounce = 2500; /* LOS def to 2.5s AT&T TR54016*/
+static int aisalarmdebounce = 2500; /* AIS(blue) def to 2.5s AT&T TR54016*/
+static int yelalarmdebounce = 500; /* RAI(yellow) def to 0.5s AT&T guide */
+static char *default_linemode = "t1"; /* 'e1', 't1', or 'j1' */
+static int latency = WCXB_DEFAULT_LATENCY;
+static int max_latency = WCXB_DEFAULT_MAXLATENCY;
+
+struct t43x_firm_header {
+ u8 header[6];
+ __le32 chksum;
+ u8 pad[18];
+ __le32 version;
+} __packed;
+
+static int t43x_check_for_interrupts(struct t43x *wc);
+static void t43x_check_alarms(struct t43x *wc, int span_idx);
+static void t43x_check_sigbits(struct t43x *wc, int span_idx);
+static const struct dahdi_span_ops t43x_span_ops;
+static void __t43x_set_timing_source_auto(struct t43x *wc);
+
+#ifndef VPM_SUPPORT
+static int vpmsupport;
+#else
+static int vpmsupport = 1;
+
+#include "oct6100api/oct6100_api.h"
+
+#define ECHOCAN_NUM_CHANS 128
+
+#define FLAGBIT_DTMF 1
+#define FLAGBIT_MUTE 2
+#define FLAGBIT_ECHO 3
+#define FLAGBIT_ALAW 4
+
+#define OCT_CHIP_ID 0
+#define OCT_MAX_TDM_STREAMS 4
+#define OCT_TONEEVENT_BUFFER_SIZE 128
+#define SOUT_STREAM 1
+#define RIN_STREAM 0
+#define SIN_STREAM 2
+
+static void t43x_vpm_init(struct t43x *wc);
+static void echocan_free(struct dahdi_chan *chan,
+ struct dahdi_echocan_state *ec);
+static const struct dahdi_echocan_features vpm_ec_features = {
+ .NLP_automatic = 1,
+ .CED_tx_detect = 1,
+ .CED_rx_detect = 1,
+};
+static const struct dahdi_echocan_ops vpm_ec_ops = {
+ .echocan_free = echocan_free,
+};
+
+struct vpm450m {
+ tPOCT6100_INSTANCE_API pApiInstance;
+ struct oct612x_context context;
+ UINT32 aulEchoChanHndl[ECHOCAN_NUM_CHANS];
+ int ecmode[ECHOCAN_NUM_CHANS];
+ unsigned long chanflags[ECHOCAN_NUM_CHANS];
+};
+
+static int t43x_oct612x_write(struct oct612x_context *context,
+ u32 address, u16 value)
+{
+ struct t43x *wc = dev_get_drvdata(context->dev);
+ wcxb_set_echocan_reg(&wc->xb, address, value);
+ return 0;
+}
+
+static int t43x_oct612x_read(struct oct612x_context *context, u32 address,
+ u16 *value)
+{
+ struct t43x *wc = dev_get_drvdata(context->dev);
+ *value = wcxb_get_echocan_reg(&wc->xb, address);
+ return 0;
+}
+
+static int t43x_oct612x_write_smear(struct oct612x_context *context,
+ u32 address, u16 value, size_t count)
+{
+ unsigned int i;
+ struct t43x *wc = dev_get_drvdata(context->dev);
+ for (i = 0; i < count; ++i)
+ wcxb_set_echocan_reg(&wc->xb, address + (i << 1), value);
+ return 0;
+}
+
+static int t43x_oct612x_write_burst(struct oct612x_context *context,
+ u32 address, const u16 *buffer,
+ size_t count)
+{
+ unsigned int i;
+ struct t43x *wc = dev_get_drvdata(context->dev);
+ for (i = 0; i < count; ++i)
+ wcxb_set_echocan_reg(&wc->xb, address + (i << 1), buffer[i]);
+ return 0;
+}
+
+static int t43x_oct612x_read_burst(struct oct612x_context *context,
+ u32 address, u16 *buffer, size_t count)
+{
+ unsigned int i;
+ struct t43x *wc = dev_get_drvdata(context->dev);
+ for (i = 0; i < count; ++i)
+ buffer[i] = wcxb_get_echocan_reg(&wc->xb, address + (i << 1));
+ return 0;
+}
+
+static const struct oct612x_ops t43x_oct612x_ops = {
+ .write = t43x_oct612x_write,
+ .read = t43x_oct612x_read,
+ .write_smear = t43x_oct612x_write_smear,
+ .write_burst = t43x_oct612x_write_burst,
+ .read_burst = t43x_oct612x_read_burst,
+};
+
+static void vpm450m_setecmode(struct vpm450m *vpm450m, int channel, int mode)
+{
+ tOCT6100_CHANNEL_MODIFY *modify;
+ UINT32 ulResult;
+
+ if (vpm450m->ecmode[channel] == mode)
+ return;
+ modify = kzalloc(sizeof(tOCT6100_CHANNEL_MODIFY), GFP_ATOMIC);
+ if (!modify) {
+ pr_notice("Unable to allocate memory for setec!\n");
+ return;
+ }
+ Oct6100ChannelModifyDef(modify);
+ modify->ulEchoOperationMode = mode;
+ modify->ulChannelHndl = vpm450m->aulEchoChanHndl[channel];
+ ulResult = Oct6100ChannelModify(vpm450m->pApiInstance, modify);
+ if (ulResult != GENERIC_OK) {
+ pr_notice("Failed to apply echo can changes on channel %d %d %08x!\n",
+ vpm450m->aulEchoChanHndl[channel], channel, ulResult);
+ } else {
+#ifdef OCTASIC_DEBUG
+ pr_debug("Echo can on channel %d set to %d\n", channel, mode);
+#endif
+ vpm450m->ecmode[channel] = mode;
+ }
+ kfree(modify);
+}
+
+static void vpm450m_set_alaw_companding(struct vpm450m *vpm450m, int channel,
+ bool alaw)
+{
+ tOCT6100_CHANNEL_MODIFY *modify;
+ UINT32 ulResult;
+ UINT32 law_to_use = (alaw) ? cOCT6100_PCM_A_LAW :
+ cOCT6100_PCM_U_LAW;
+
+ /* If we're already in this companding mode, no need to do anything. */
+ if (alaw == (test_bit(FLAGBIT_ALAW, &vpm450m->chanflags[channel]) > 0))
+ return;
+
+ modify = kzalloc(sizeof(tOCT6100_CHANNEL_MODIFY), GFP_ATOMIC);
+ if (!modify) {
+ pr_notice("Unable to allocate memory for setec!\n");
+ return;
+ }
+
+ Oct6100ChannelModifyDef(modify);
+ modify->ulChannelHndl = vpm450m->aulEchoChanHndl[channel];
+ modify->fTdmConfigModified = TRUE;
+ modify->TdmConfig.ulSinPcmLaw = law_to_use;
+ modify->TdmConfig.ulRinPcmLaw = law_to_use;
+ modify->TdmConfig.ulSoutPcmLaw = law_to_use;
+ modify->TdmConfig.ulRoutPcmLaw = law_to_use;
+ ulResult = Oct6100ChannelModify(vpm450m->pApiInstance, modify);
+ if (ulResult != GENERIC_OK) {
+ pr_notice("Failed to apply echo can changes on channel %d %d %08x!\n",
+ vpm450m->aulEchoChanHndl[channel], channel, ulResult);
+ } else {
+ if (debug) {
+ pr_info("Changed companding on channel %d to %s.\n",
+ channel, (alaw) ? "alaw" : "ulaw");
+ }
+ if (alaw)
+ set_bit(FLAGBIT_ALAW, &vpm450m->chanflags[channel]);
+ else
+ clear_bit(FLAGBIT_ALAW, &vpm450m->chanflags[channel]);
+ }
+ kfree(modify);
+}
+
+static void vpm450m_setec(struct vpm450m *vpm450m, int channel, int eclen)
+{
+ if (eclen) {
+ set_bit(FLAGBIT_ECHO, &vpm450m->chanflags[channel]);
+ vpm450m_setecmode(vpm450m, channel,
+ cOCT6100_ECHO_OP_MODE_NORMAL);
+ } else {
+ unsigned long *flags = &vpm450m->chanflags[channel];
+ clear_bit(FLAGBIT_ECHO, &vpm450m->chanflags[channel]);
+ if (test_bit(FLAGBIT_DTMF, flags) ||
+ test_bit(FLAGBIT_MUTE, flags)) {
+ vpm450m_setecmode(vpm450m, channel,
+ cOCT6100_ECHO_OP_MODE_HT_RESET);
+ } else {
+ vpm450m_setecmode(vpm450m, channel,
+ cOCT6100_ECHO_OP_MODE_POWER_DOWN);
+ }
+ }
+}
+
+static UINT32 tdmmode_chan_to_slot_map(int channel)
+{
+ /* Four phases on the tdm bus, skip three of them per channel */
+ /* Due to a bug in the octasic, we had to move the data onto phase 2 */
+ return 1 + ((channel % 32) * 4) + (channel / 32);
+}
+
+static int echocan_initialize_channel(
+ struct vpm450m *vpm, int channel, int mode)
+{
+ tOCT6100_CHANNEL_OPEN ChannelOpen;
+ UINT32 law_to_use = (mode) ? cOCT6100_PCM_A_LAW :
+ cOCT6100_PCM_U_LAW;
+ UINT32 tdmslot_setting;
+ UINT32 ulResult;
+
+ tdmslot_setting = tdmmode_chan_to_slot_map(channel);
+
+ /* Fill Open channel structure with defaults */
+ Oct6100ChannelOpenDef(&ChannelOpen);
+
+ /* Assign the handle memory.*/
+ ChannelOpen.pulChannelHndl = &vpm->aulEchoChanHndl[channel];
+ ChannelOpen.ulUserChanId = channel;
+ /* Enable Tone disabling for Fax and Modems */
+ ChannelOpen.fEnableToneDisabler = TRUE;
+
+ /* Passthrough TDM data by default, no echocan */
+ ChannelOpen.ulEchoOperationMode = cOCT6100_ECHO_OP_MODE_POWER_DOWN;
+
+ /* Configure the TDM settings.*/
+ /* Input from the framer */
+ ChannelOpen.TdmConfig.ulSinStream = SIN_STREAM;
+ ChannelOpen.TdmConfig.ulSinTimeslot = tdmslot_setting;
+ ChannelOpen.TdmConfig.ulSinPcmLaw = law_to_use;
+
+ /* Input from the Host (pre-framer) */
+ ChannelOpen.TdmConfig.ulRinStream = RIN_STREAM;
+ ChannelOpen.TdmConfig.ulRinTimeslot = tdmslot_setting;
+ ChannelOpen.TdmConfig.ulRinPcmLaw = law_to_use;
+
+ /* Output to the Host */
+ ChannelOpen.TdmConfig.ulSoutStream = SOUT_STREAM;
+ ChannelOpen.TdmConfig.ulSoutTimeslot = tdmslot_setting;
+ ChannelOpen.TdmConfig.ulSoutPcmLaw = law_to_use;
+
+ /* From asterisk after echo-cancellation - goes nowhere */
+ ChannelOpen.TdmConfig.ulRoutStream = cOCT6100_UNASSIGNED;
+ ChannelOpen.TdmConfig.ulRoutTimeslot = cOCT6100_UNASSIGNED;
+ ChannelOpen.TdmConfig.ulRoutPcmLaw = law_to_use;
+
+ /* Set the desired VQE features.*/
+ ChannelOpen.VqeConfig.fEnableNlp = TRUE;
+ ChannelOpen.VqeConfig.fRinDcOffsetRemoval = TRUE;
+ ChannelOpen.VqeConfig.fSinDcOffsetRemoval = TRUE;
+ ChannelOpen.VqeConfig.ulComfortNoiseMode =
+ cOCT6100_COMFORT_NOISE_NORMAL;
+
+ /* Open the channel.*/
+ ulResult = Oct6100ChannelOpen(vpm->pApiInstance, &ChannelOpen);
+
+ return ulResult;
+}
+
+static struct vpm450m *init_vpm450m(struct t43x *wc, int *laws, int numspans,
+ const struct firmware *firmware)
+{
+ tOCT6100_CHIP_OPEN *ChipOpen;
+ tOCT6100_GET_INSTANCE_SIZE InstanceSize;
+ tOCT6100_CHANNEL_OPEN *ChannelOpen;
+ UINT32 ulResult;
+ struct vpm450m *vpm450m;
+ int x, i;
+
+ vpm450m = kzalloc(sizeof(struct vpm450m), GFP_KERNEL);
+ if (!vpm450m) {
+ dev_info(&wc->xb.pdev->dev,
+ "Unable to allocate vpm450m struct\n");
+ return NULL;
+ }
+
+ vpm450m->context.dev = &wc->xb.pdev->dev;
+ vpm450m->context.ops = &t43x_oct612x_ops;
+
+ ChipOpen = kzalloc(sizeof(tOCT6100_CHIP_OPEN), GFP_KERNEL);
+ if (!ChipOpen) {
+ dev_info(&wc->xb.pdev->dev, "Unable to allocate ChipOpen\n");
+ kfree(vpm450m);
+ return NULL;
+ }
+
+ ChannelOpen = kzalloc(sizeof(tOCT6100_CHANNEL_OPEN), GFP_KERNEL);
+ if (!ChannelOpen) {
+ dev_info(&wc->xb.pdev->dev, "Unable to allocate ChannelOpen\n");
+ kfree(vpm450m);
+ kfree(ChipOpen);
+ return NULL;
+ }
+
+ for (x = 0; x < ARRAY_SIZE(vpm450m->ecmode); x++)
+ vpm450m->ecmode[x] = -1;
+
+ dev_info(&wc->xb.pdev->dev, "Echo cancellation for %d channels\n",
+ wc->numspans * 32);
+
+ Oct6100ChipOpenDef(ChipOpen);
+ ChipOpen->pProcessContext = &vpm450m->context;
+
+ /* Change default parameters as needed */
+ /* upclk oscillator is at 33.33 Mhz */
+ ChipOpen->ulUpclkFreq = cOCT6100_UPCLK_FREQ_33_33_MHZ;
+
+ /* mclk will be generated by internal PLL at 133 Mhz */
+ ChipOpen->fEnableMemClkOut = TRUE;
+ ChipOpen->ulMemClkFreq = cOCT6100_MCLK_FREQ_133_MHZ;
+
+ /* User defined Chip ID.*/
+ ChipOpen->ulUserChipId = OCT_CHIP_ID;
+
+ /* Set the maximums that the chip needs to support */
+ ChipOpen->ulMaxChannels = wc->numspans * 32;
+ ChipOpen->ulMaxTdmStreams = OCT_MAX_TDM_STREAMS;
+
+ /* External Memory Settings */
+ /* Use DDR memory.*/
+ ChipOpen->ulMemoryType = cOCT6100_MEM_TYPE_DDR;
+ ChipOpen->ulNumMemoryChips = 1;
+ ChipOpen->ulMemoryChipSize = cOCT6100_MEMORY_CHIP_SIZE_32MB;
+
+ ChipOpen->pbyImageFile = (PUINT8) firmware->data;
+ ChipOpen->ulImageSize = firmware->size;
+
+ /* Set TDM data stream frequency */
+ for (i = 0; i < ChipOpen->ulMaxTdmStreams; i++)
+ ChipOpen->aulTdmStreamFreqs[i] = cOCT6100_TDM_STREAM_FREQ_8MHZ;
+
+ /* Configure TDM sampling */
+ ChipOpen->ulTdmSampling = cOCT6100_TDM_SAMPLE_AT_FALLING_EDGE;
+ /* Disable to save RAM footprint space */
+ ChipOpen->fEnableChannelRecording = false;
+
+ /* In this example we will maintain the API using polling so
+ interrupts must be disabled */
+ ChipOpen->InterruptConfig.ulErrorH100Config =
+ cOCT6100_INTERRUPT_DISABLE;
+ ChipOpen->InterruptConfig.ulErrorMemoryConfig =
+ cOCT6100_INTERRUPT_DISABLE;
+ ChipOpen->InterruptConfig.ulFatalGeneralConfig =
+ cOCT6100_INTERRUPT_DISABLE;
+ ChipOpen->InterruptConfig.ulFatalMemoryConfig =
+ cOCT6100_INTERRUPT_DISABLE;
+
+ ChipOpen->ulSoftToneEventsBufSize = OCT_TONEEVENT_BUFFER_SIZE;
+
+ /* Inserting default values into tOCT6100_GET_INSTANCE_SIZE
+ structure parameters. */
+ Oct6100GetInstanceSizeDef(&InstanceSize);
+
+ /* Reset octasic device */
+ wcxb_reset_echocan(&wc->xb);
+
+ /* Get the size of the OCT6100 instance structure. */
+ ulResult = Oct6100GetInstanceSize(ChipOpen, &InstanceSize);
+ if (ulResult != cOCT6100_ERR_OK) {
+ dev_info(&wc->xb.pdev->dev, "Unable to get instance size: %x\n",
+ ulResult);
+ return NULL;
+ }
+
+ vpm450m->pApiInstance = vmalloc(InstanceSize.ulApiInstanceSize);
+ if (!vpm450m->pApiInstance) {
+ dev_info(&wc->xb.pdev->dev,
+ "Out of memory (can't allocate %d bytes)!\n",
+ InstanceSize.ulApiInstanceSize);
+ return NULL;
+ }
+
+ /* Perform the actual configuration of the chip. */
+ wcxb_enable_echocan_dram(&wc->xb);
+ ulResult = Oct6100ChipOpen(vpm450m->pApiInstance, ChipOpen);
+ if (ulResult != cOCT6100_ERR_OK) {
+ dev_info(&wc->xb.pdev->dev, "Unable to Oct6100ChipOpen: %x\n",
+ ulResult);
+ return NULL;
+ }
+
+ /* OCT6100 is now booted and channels can be opened */
+ /* Open 31 channels/span since we're skipping the first on the VPM */
+ for (x = 0; x < numspans; x++) {
+ for (i = 0; i < 31; i++) {
+ ulResult = echocan_initialize_channel(vpm450m,
+ (x*32)+i,
+ laws[x]);
+ if (0 != ulResult) {
+ dev_info(&wc->xb.pdev->dev,
+ "Unable to echocan_initialize_channel: %d %x\n",
+ (x*32)+i, ulResult);
+ return NULL;
+ } else if (laws[x]) {
+ set_bit(FLAGBIT_ALAW,
+ &vpm450m->chanflags[(x*32)+i]);
+ }
+ }
+ }
+
+ if (vpmsupport != 0)
+ wcxb_enable_echocan(&wc->xb);
+
+ kfree(ChipOpen);
+ kfree(ChannelOpen);
+ return vpm450m;
+}
+
+static void release_vpm450m(struct vpm450m *vpm450m)
+{
+ UINT32 ulResult;
+ tOCT6100_CHIP_CLOSE ChipClose;
+
+ Oct6100ChipCloseDef(&ChipClose);
+ ulResult = Oct6100ChipClose(vpm450m->pApiInstance, &ChipClose);
+ if (ulResult != cOCT6100_ERR_OK)
+ pr_notice("Failed to close chip, code %08x!\n", ulResult);
+ vfree(vpm450m->pApiInstance);
+ kfree(vpm450m);
+}
+
+static const char *__t43x_echocan_name(struct t43x *wc)
+{
+ if (wc->vpm)
+ return wc->vpm_name;
+ else
+ return NULL;
+}
+
+static const char *t43x_echocan_name(const struct dahdi_chan *chan)
+{
+ struct t43x *wc = chan->pvt;
+ return __t43x_echocan_name(wc);
+}
+
+static int t43x_echocan_create(struct dahdi_chan *chan,
+ struct dahdi_echocanparams *ecp,
+ struct dahdi_echocanparam *p,
+ struct dahdi_echocan_state **ec)
+{
+ struct t43x *wc = chan->pvt;
+ struct t43x_span *ts = container_of(chan->span, struct t43x_span, span);
+ int channel = chan->chanpos - 1;
+ const struct dahdi_echocan_ops *ops;
+ const struct dahdi_echocan_features *features;
+ const bool alaw = (chan->span->deflaw == 2);
+
+ if (!vpmsupport || !wc->vpm)
+ return -ENODEV;
+
+ ops = &vpm_ec_ops;
+ features = &vpm_ec_features;
+
+ if (ecp->param_count > 0) {
+ dev_warn(&wc->xb.pdev->dev,
+ "%s echo canceller does not support parameters; failing request\n",
+ chan->ec_factory->get_name(chan));
+ return -EINVAL;
+ }
+
+ *ec = ts->ec[channel];
+ (*ec)->ops = ops;
+ (*ec)->features = *features;
+
+ channel += (32*chan->span->offset);
+ vpm450m_set_alaw_companding(wc->vpm, channel, alaw);
+ vpm450m_setec(wc->vpm, channel, ecp->tap_length);
+ return 0;
+}
+
+static void echocan_free(struct dahdi_chan *chan,
+ struct dahdi_echocan_state *ec)
+{
+ struct t43x *wc = chan->pvt;
+ int channel = chan->chanpos - 1;
+ if (!wc->vpm)
+ return;
+ memset(ec, 0, sizeof(*ec));
+ channel += (32*chan->span->offset);
+ vpm450m_setec(wc->vpm, channel, 0);
+}
+
+static void t43x_vpm_init(struct t43x *wc)
+{
+ int laws[8] = {0, };
+ int x;
+
+ struct firmware embedded_firmware;
+ const struct firmware *firmware = &embedded_firmware;
+#if !defined(HOTPLUG_FIRMWARE)
+ extern void _binary_dahdi_fw_oct6114_064_bin_size;
+ extern u8 _binary_dahdi_fw_oct6114_064_bin_start[];
+ extern void _binary_dahdi_fw_oct6114_128_bin_size;
+ extern u8 _binary_dahdi_fw_oct6114_128_bin_start[];
+#else
+ static const char oct064_firmware[] = "dahdi-fw-oct6114-064.bin";
+ static const char oct128_firmware[] = "dahdi-fw-oct6114-128.bin";
+ const char *oct_firmware;
+#endif
+
+ if (!vpmsupport) {
+ dev_info(&wc->xb.pdev->dev, "VPM450: Support Disabled\n");
+ return;
+ }
+
+#if defined(HOTPLUG_FIRMWARE)
+ if (wc->numspans == 2) {
+ wc->vpm_name = "VPMOCT064";
+ oct_firmware = oct064_firmware;
+ } else {
+ wc->vpm_name = "VPMOCT128";
+ oct_firmware = oct128_firmware;
+ }
+ if ((request_firmware(&firmware, oct_firmware, &wc->xb.pdev->dev) != 0)
+ || !firmware) {
+ dev_notice(&wc->xb.pdev->dev,
+ "VPM450: firmware %s not available from userspace\n",
+ oct_firmware);
+ return;
+ }
+#else
+ /* Yes... this is weird. objcopy gives us a symbol containing
+ the size of the firmware, not a pointer a variable containing
+ the size. The only way we can get the value of the symbol
+ is to take its address, so we define it as a pointer and
+ then cast that value to the proper type.
+ */
+ if (wc->numspans == 2) {
+ embedded_firmware.data = _binary_dahdi_fw_oct6114_064_bin_start;
+ embedded_firmware.size =
+ (size_t)&_binary_dahdi_fw_oct6114_064_bin_size;
+ } else {
+ embedded_firmware.size =
+ (size_t)&_binary_dahdi_fw_oct6114_128_bin_size;
+ embedded_firmware.data = _binary_dahdi_fw_oct6114_128_bin_start;
+ }
+#endif
+
+ /* Setup alaw vs ulaw rules */
+ for (x = 0; x < wc->numspans; x++) {
+ if (wc->tspans[x]->span.channels > 24)
+ laws[x] = 1;
+ }
+
+ wc->vpm = init_vpm450m(wc, laws, wc->numspans, firmware);
+
+ if (!wc->vpm) {
+ dev_notice(&wc->xb.pdev->dev, "VPM450: Failed to initialize\n");
+ if (firmware != &embedded_firmware)
+ release_firmware(firmware);
+ return;
+ }
+
+ if (firmware != &embedded_firmware)
+ release_firmware(firmware);
+
+ dev_info(&wc->xb.pdev->dev,
+ "VPM450: Present and operational servicing %d span(s)\n",
+ wc->numspans);
+
+}
+#endif /* VPM_SUPPORT */
+
+static int t43x_clear_maint(struct dahdi_span *span);
+
+static DEFINE_MUTEX(card_list_lock);
+static LIST_HEAD(card_list);
+
+struct t43x_desc {
+ const char *name;
+};
+
+static const struct t43x_desc te435 = {"Wildcard TE435"}; /* pci express quad */
+static const struct t43x_desc te235 = {"Wildcard TE235"}; /* pci express dual */
+
+static int __t43x_pci_get(struct t43x *wc, unsigned int addr)
+{
+ unsigned int res = ioread8(wc->xb.membase + addr);
+ return res;
+}
+
+static inline int __t43x_pci_set(struct t43x *wc, unsigned int addr, int val)
+{
+ iowrite8(val, wc->xb.membase + addr);
+ __t43x_pci_get(wc, 0);
+ return 0;
+}
+
+static inline int t43x_pci_get(struct t43x *wc, int addr)
+{
+ unsigned int ret;
+ unsigned long flags;
+
+ spin_lock_irqsave(&wc->reglock, flags);
+ ret = __t43x_pci_get(wc, addr);
+ spin_unlock_irqrestore(&wc->reglock, flags);
+ return ret;
+}
+
+static inline int t43x_pci_set(struct t43x *wc, int addr, int val)
+{
+ unsigned long flags;
+ unsigned int ret;
+ spin_lock_irqsave(&wc->reglock, flags);
+ ret = __t43x_pci_set(wc, addr, val);
+ spin_unlock_irqrestore(&wc->reglock, flags);
+ return ret;
+}
+
+static inline int
+__t43x_framer_set(struct t43x *wc, int unit, int addr, int val)
+{
+ return __t43x_pci_set(wc, FRAMER_BASE + (unit << 8) + addr, val);
+}
+
+static inline int t43x_framer_set(struct t43x *wc, int unit, int addr, int val)
+{
+ return t43x_pci_set(wc, FRAMER_BASE + (unit << 8) + addr, val);
+}
+
+static inline int __t43x_framer_get(struct t43x *wc, int unit, int addr)
+{
+ return __t43x_pci_get(wc, FRAMER_BASE + (unit << 8) + addr);
+}
+
+static inline int t43x_framer_get(struct t43x *wc, int unit, int addr)
+{
+ return t43x_pci_get(wc, FRAMER_BASE + (unit << 8) + addr);
+}
+
+static void t43x_framer_reset(struct t43x *wc)
+{
+ /*
+ * When the framer is reset, RCLK will stop. The FPGA must be switched
+ * to it's internal clock when this happens, but it's only safe to
+ * switch the clock source on the FPGA when the DMA engine is stopped.
+ *
+ */
+ wcxb_stop_dma(&wc->xb);
+ wcxb_wait_for_stop(&wc->xb, 50);
+ wcxb_set_clksrc(&wc->xb, WCXB_CLOCK_SELF);
+ wcxb_gpio_clear(&wc->xb, FALC_CPU_RESET);
+ msleep_interruptible(100);
+ wcxb_gpio_set(&wc->xb, FALC_CPU_RESET);
+}
+
+static void t43x_setleds(struct t43x *wc, u32 leds)
+{
+ wcxb_gpio_set(&wc->xb, leds & LED_MASK);
+ wcxb_gpio_clear(&wc->xb, ~leds & LED_MASK);
+}
+
+static void t43x_set_cas_mode(struct t43x *wc, int span_idx)
+{
+ struct t43x_span *ts = wc->tspans[span_idx];
+ int fidx = (wc->numspans == 2) ? span_idx+1 : span_idx;
+ int i, offset;
+ int reg;
+ unsigned long flags;
+ bool span_has_cas_channel = false;
+
+ if (debug)
+ dev_info(&wc->xb.pdev->dev, "%s span: %d\n", __func__,
+ span_idx);
+
+ if (dahdi_is_e1_span(&ts->span)) {
+ span_has_cas_channel = !(ts->span.lineconfig&DAHDI_CONFIG_CCS);
+ } else {
+ unsigned char ccb[3] = {0, 0, 0};
+ /* Sort out channels that use CAS signalling */
+ for (i = 0; i < ts->span.channels; i++) {
+ offset = i/8;
+ if (offset >= ARRAY_SIZE(ccb)) {
+ WARN_ON(1);
+ break;
+ }
+ if (ts->span.chans[i]->flags & DAHDI_FLAG_CLEAR)
+ ccb[offset] |= 1 << (7 - (i % 8));
+ else
+ ccb[offset] &= ~(1 << (7 - (i % 8)));
+ }
+
+ spin_lock_irqsave(&wc->reglock, flags);
+ __t43x_framer_set(wc, fidx, CCB1, ccb[0]);
+ __t43x_framer_set(wc, fidx, CCB2, ccb[1]);
+ __t43x_framer_set(wc, fidx, CCB3, ccb[2]);
+ spin_unlock_irqrestore(&wc->reglock, flags);
+
+ if ((~ccb[0]) | (~ccb[1]) | (~ccb[2]))
+ span_has_cas_channel = true;
+ }
+
+ /* Unmask CAS RX interrupt if any single channel is in CAS mode */
+ /* This interrupt is called RSC in T1 and CASC in E1 */
+ spin_lock_irqsave(&wc->reglock, flags);
+ reg = __t43x_framer_get(wc, fidx, IMR0);
+ if (span_has_cas_channel)
+ __t43x_framer_set(wc, fidx, IMR0, reg & ~0x08);
+ else
+ __t43x_framer_set(wc, fidx, IMR0, reg | 0x08);
+ spin_unlock_irqrestore(&wc->reglock, flags);
+}
+
+/**
+ * _t43x_free_channels - Free the memory allocated for the channels.
+ *
+ * Must be called with wc->reglock held.
+ *
+ */
+static void _t43x_free_channels(struct t43x *wc)
+{
+ unsigned int x, y;
+
+ for (x = 0; x < ARRAY_SIZE(wc->tspans); x++) {
+ if (!wc->tspans[x])
+ continue;
+ for (y = 0; y < ARRAY_SIZE(wc->tspans[x]->chans); y++) {
+ kfree(wc->tspans[x]->chans[y]);
+ kfree(wc->tspans[x]->ec[y]);
+ }
+ kfree(wc->tspans[x]);
+ }
+}
+
+static void free_wc(struct t43x *wc)
+{
+ unsigned long flags;
+ LIST_HEAD(list);
+
+ mutex_lock(&card_list_lock);
+ list_del(&wc->card_node);
+ mutex_unlock(&card_list_lock);
+
+ spin_lock_irqsave(&wc->reglock, flags);
+ _t43x_free_channels(wc);
+ spin_unlock_irqrestore(&wc->reglock, flags);
+
+ if (wc->wq)
+ destroy_workqueue(wc->wq);
+ kfree(wc->ddev->location);
+ kfree(wc->ddev->devicetype);
+ kfree(wc->ddev->hardware_id);
+ if (wc->ddev)
+ dahdi_free_device(wc->ddev);
+ kfree(wc);
+}
+
+static void t43x_serial_setup(struct t43x *wc)
+{
+ unsigned long flags;
+ int slot, fidx;
+
+ dev_info(&wc->xb.pdev->dev,
+ "Setting up global serial parameters for card %d\n", wc->num);
+
+ t43x_framer_reset(wc);
+
+ spin_lock_irqsave(&wc->reglock, flags);
+ /* GPC1: Multiplex mode enabled, FSC is output, active low, RCLK from
+ * channel 0 */
+ __t43x_framer_set(wc, 0, 0x85, 0xe0);
+ /* GPC3: Enable Multi Purpose Switches */
+ __t43x_framer_set(wc, 0, 0xd3, 0xa1);
+ /* GPC4: Enable Multi Purpose Switches */
+ __t43x_framer_set(wc, 0, 0xd4, 0x83);
+ /* GPC5: Enable Multi Purpose Switches */
+ __t43x_framer_set(wc, 0, 0xd5, 0xe5);
+ /* GPC4: Enable Multi Purpose Switches */
+ __t43x_framer_set(wc, 0, 0xd6, 0x87);
+ /* IPC: Interrupt push/pull active low, 8KHz ref clk */
+ __t43x_framer_set(wc, 0, 0x08, 0x05);
+
+ /* Global clocks (8.192 Mhz CLK) */
+ __t43x_framer_set(wc, 0, 0x92, 0x00);
+ __t43x_framer_set(wc, 0, 0x93, 0x18);
+ __t43x_framer_set(wc, 0, 0x94, 0xfb);
+ __t43x_framer_set(wc, 0, 0x95, 0x0b);
+ __t43x_framer_set(wc, 0, 0x96, 0x00);
+ __t43x_framer_set(wc, 0, 0x97, 0x0b);
+ __t43x_framer_set(wc, 0, 0x98, 0xdb);
+ __t43x_framer_set(wc, 0, 0x99, 0xdf);
+
+ spin_unlock_irqrestore(&wc->reglock, flags);
+
+ for (fidx = 0; fidx < 4; fidx++) {
+ /* For dual-span, put the second and third framers
+ * onto the first and second timeslots */
+ if (wc->numspans == 2)
+ slot = (fidx - 1) & 3;
+ else
+ slot = fidx;
+ spin_lock_irqsave(&wc->reglock, flags);
+
+ /* Configure interrupts */
+
+ /* GCR: Interrupt on Activation/Deactivation of AIX, LOS */
+ __t43x_framer_set(wc, fidx, 0x46, 0xc0);
+
+ /* Configure system interface */
+
+ /* SIC1: 8.192 Mhz clock/bus, double buffer receive /
+ * transmit, byte interleaved */
+ __t43x_framer_set(wc, fidx, 0x3e, 0xc2);
+ /* SIC2: No FFS, no CRB, SSC2 = 0, phase = unit */
+ __t43x_framer_set(wc, fidx, 0x3f, (slot << 1));
+
+ /* SIC3: Edges for capture - original rx rising edge */
+ __t43x_framer_set(wc, fidx, 0x40, 0x04);
+ /* SIC4: CES high, SYPR opposite edge */
+ __t43x_framer_set(wc, fidx, 0x2a, 0x06);
+
+#ifndef RPC_RCLK
+ /* CMR1: RCLK is at 8.192 Mhz dejittered */
+ __t43x_framer_set(wc, fidx, 0x44, 0x30);
+#else
+ /* CMR1: RCLK is at 8.192 Mhz dejittered, ref clock is this
+ * channel */
+ __t43x_framer_set(wc, fidx, 0x44, 0x38 | (fidx << 6));
+#endif
+
+ /* CMR2: We provide sync and clock for tx and rx. */
+ __t43x_framer_set(wc, fidx, 0x45, 0x00);
+
+ /* XC0: Normal operation of Sa-bits */
+ __t43x_framer_set(wc, fidx, 0x22, 0x07);
+ __t43x_framer_set(wc, fidx, 0x23, 0xfa); /* XC1 */
+
+ __t43x_framer_set(wc, fidx, 0x24, 0x07); /* RC0 */
+ __t43x_framer_set(wc, fidx, 0x25, 0xfa); /* RC1 */
+
+ /* Configure ports */
+ /* PC1: SPYR/SPYX input on RPA/XPA */
+ __t43x_framer_set(wc, fidx, 0x80, 0x00);
+ /* PC2: Unused stuff */
+ __t43x_framer_set(wc, fidx, 0x81, 0xBB);
+#ifndef RPC_RCLK
+ /* PC3: Unused stuff */
+ __t43x_framer_set(wc, fidx, 0x82, 0xBB);
+#else
+ /* PC3: RPC is RCLK, XPC is low output */
+ __t43x_framer_set(wc, fidx, 0x82, 0xFB);
+#endif
+ /* PC4: Unused stuff */
+ __t43x_framer_set(wc, fidx, 0x83, 0xBB);
+ /* PC5: XMFS active low, SCLKR is input, RCLK is output */
+ __t43x_framer_set(wc, fidx, 0x84, 0x01);
+ __t43x_framer_set(wc, fidx, 0x3b, 0x00); /* Clear LCR1 */
+
+ /* Make sure unused ports are set to T1 configuration as a
+ * default. This is required in order to make clock recovery
+ * works on spans that are actually configured. */
+
+ __t43x_framer_set(wc, fidx, 0x1c, 0xf0);
+ __t43x_framer_set(wc, fidx, 0x1d, 0x9c);
+ __t43x_framer_set(wc, fidx, 0x1e, 0x20);
+ __t43x_framer_set(wc, fidx, 0x20, 0x0c);
+ /* FMR5: Enable RBS mode */
+ __t43x_framer_set(wc, fidx, 0x21, 0x40);
+
+ __t43x_framer_set(wc, fidx, 0x36, 0x08);
+ __t43x_framer_set(wc, fidx, 0x37, 0xf0);
+ __t43x_framer_set(wc, fidx, 0x3a, 0x21);
+
+ __t43x_framer_set(wc, fidx, 0x02, 0x50);
+ __t43x_framer_set(wc, fidx, 0x02, 0x00);
+
+ __t43x_framer_set(wc, fidx, 0x38, 0x0a);
+ __t43x_framer_set(wc, fidx, 0x39, 0x15);
+ /* Tri-state the TX output for the port */
+ __t43x_framer_set(wc, fidx, 0x28, 0x40);
+
+ spin_unlock_irqrestore(&wc->reglock, flags);
+ }
+}
+
+/**
+ * t43x_span_assigned - Called when the span is assigned by DAHDI.
+ * @span: Span that has been assigned.
+ *
+ * When this function is called, the span has a valid spanno and all the
+ * channels on the span have valid channel numbers assigned.
+ *
+ * This function is necessary because a device may be registered, and
+ * then user space may then later decide to assign span numbers and the
+ * channel numbers.
+ *
+ */
+static void t43x_span_assigned(struct dahdi_span *span)
+{
+ struct t43x_span *tspan = container_of(span, struct t43x_span, span);
+ struct t43x *wc = tspan->owner;
+ struct dahdi_span *pos;
+ unsigned int unassigned_spans = 0;
+
+ if (debug)
+ dev_info(&wc->xb.pdev->dev, "%s\n", __func__);
+
+ span->alarms = DAHDI_ALARM_NONE;
+
+ /* We use this to make sure all the spans are assigned before
+ * running the serial setup. */
+ list_for_each_entry(pos, &wc->ddev->spans, device_node) {
+ if (!test_bit(DAHDI_FLAGBIT_REGISTERED, &pos->flags))
+ ++unassigned_spans;
+ }
+
+ if (0 == unassigned_spans) {
+ /* Now all the spans are assigned so we can go ahead and start
+ * things up. */
+ t43x_serial_setup(wc);
+ }
+}
+
+static int syncsrc;
+static int syncnum;
+static int syncspan;
+static DEFINE_SPINLOCK(synclock);
+
+static void __t43x_set_rclk_src(struct t43x *wc, int span)
+{
+#ifndef RPC_RCLK
+ int cmr1 = 0x38; /* Clock Mode: RCLK sourced by DCO-R1
+ by default, Disable Clock-Switching */
+ int fidx;
+
+ if (2 == wc->numspans) {
+ u8 reg;
+
+ /* Since the clock always comes from the first span (which is
+ * not connected to a physical port on the dual span) we can
+ * always set the framer mode register to match whatever span
+ * we're currently sourcing the timing from. This ensures that
+ * the DCO-R is always expecting the right clock speed from the
+ * line. */
+
+ fidx = span+1;
+
+ reg = __t43x_framer_get(wc, fidx, 0x1d);
+ __t43x_framer_set(wc, 0, 0x1d, reg);
+
+ reg = __t43x_framer_get(wc, fidx, 0x1e);
+ __t43x_framer_set(wc, 0, 0x1e, reg);
+
+ } else {
+ fidx = span;
+ }
+
+ cmr1 |= (fidx) << 6;
+ __t43x_framer_set(wc, 0, 0x44, cmr1);
+#else
+ int fidx = (2 == wc->numspans) ? span+1 : span;
+ int gpc1 = __t43x_framer_get(wc, 0, 0x85);
+
+ gpc1 &= ~3;
+ gpc1 |= fidx & 3;
+
+ t43x_framer_set(wc, 0, 0x85, gpc1);
+#endif
+ dev_info(&wc->xb.pdev->dev, "RCLK source set to span %d\n", span+1);
+}
+
+/* This is called from the workqueue to wait for the TDM engine stop */
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 20)
+static void t43x_clksrc_work_fn(void *data)
+{
+ struct t43x_clksrc_work *work = data;
+#else
+static void t43x_clksrc_work_fn(struct work_struct *data)
+{
+ struct t43x_clksrc_work *work = container_of(to_delayed_work(data),
+ struct t43x_clksrc_work, work);
+#endif
+ struct t43x *wc = container_of(work, struct t43x, clksrc_work);
+
+ if (debug) {
+ dev_info(&wc->xb.pdev->dev,
+ "t43x_clksrc_work() called from queue\n");
+ }
+
+ if (wcxb_is_stopped(&wc->xb)) {
+
+ /* Set new clock select */
+ if (work->is_timing_master)
+ wcxb_enable_timing_header_driver(&wc->xb);
+ else
+ wcxb_disable_timing_header_driver(&wc->xb);
+ wcxb_set_clksrc(&wc->xb, work->clksrc);
+
+ /* Restart DMA processing */
+ wcxb_start(&wc->xb);
+ } else {
+ /* Stop DMA again in case DMA underrun int restarted it */
+ wcxb_stop_dma(&wc->xb);
+ queue_delayed_work(wc->wq, &work->work, msecs_to_jiffies(10));
+ }
+}
+
+/**
+ * __t43x_set_sclk_src - Change the current source of the source clock.
+ * @wc: The board to change the clock source on.
+ * @mode: The clock mode that we would like to move to.
+ * @master: If true, drive the clock on the timing header.
+ *
+ * The clock srouce cannot be changed while DMA is active, so this function
+ * will stop the DMA, then queue a delayed work item in order to come back and
+ * check that DMA was actually stopped before changing the source of the clock.
+ *
+ */
+static void
+__t43x_set_sclk_src(struct t43x *wc, enum wcxb_clock_sources mode, bool master)
+{
+ struct t43x_clksrc_work *const work = &wc->clksrc_work;
+ unsigned long flags;
+ bool changed = false;
+
+ /* Cannot drive the clock on the header while also slaving from it. */
+ WARN_ON(master && (mode == WCXB_CLOCK_SLAVE));
+
+ spin_lock_irqsave(&work->lock, flags);
+ if (!delayed_work_pending(&work->work)) {
+ /* We want to check the actual settings. */
+ changed = (wcxb_get_clksrc(&wc->xb) != mode) ||
+ (wcxb_is_timing_header_driver_enabled(&wc->xb) != master);
+ } else {
+ /* Otherwise, we'll check if delayed work is going to set it to
+ * the same value. */
+
+ changed = (work->clksrc != mode) ||
+ (work->is_timing_master != master);
+ }
+ if (changed) {
+ work->clksrc = mode;
+ work->is_timing_master = master;
+ }
+ spin_unlock_irqrestore(&work->lock, flags);
+
+ if (!changed) {
+ if (debug)
+ dev_info(&wc->xb.pdev->dev, "Clock source is unchanged\n");
+ return;
+ }
+
+ wcxb_stop_dma(&wc->xb);
+
+ dev_dbg(&wc->xb.pdev->dev,
+ "Queueing delayed work for clock source change\n");
+
+ queue_delayed_work(wc->wq, &work->work, msecs_to_jiffies(10));
+}
+
+static ssize_t t43x_timing_master_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct t43x *wc = dev_get_drvdata(dev);
+
+ if (wcxb_is_timing_header_driver_enabled(&wc->xb))
+ return sprintf(buf, "%d\n", wc->syncsrc);
+ else
+ return sprintf(buf, "%d\n", -1);
+}
+
+static DEVICE_ATTR(timing_master, 0400, t43x_timing_master_show, NULL);
+
+static ssize_t
+dcxo_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct t43x *wc = dev_get_drvdata(dev);
+ return sprintf(buf, "0x%08x\n", ioread32be(wc->xb.membase + 0x2008));
+}
+
+static ssize_t
+dcxo_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ int ret;
+ struct t43x *wc = dev_get_drvdata(dev);
+ u32 dcxo_setting;
+ ret = sscanf(buf, "%x", &dcxo_setting);
+ iowrite32be(dcxo_setting, wc->xb.membase + 0x2008);
+ ioread32be(wc->xb.membase + 0x2008);
+ iowrite32be(dcxo_setting, wc->xb.membase + 0x2008);
+ ioread32be(wc->xb.membase + 0x2008);
+ return count;
+}
+
+static DEVICE_ATTR(dcxo, 0644, dcxo_show, dcxo_store);
+
+static void create_sysfs_files(struct t43x *wc)
+{
+ int ret;
+ ret = device_create_file(&wc->xb.pdev->dev,
+ &dev_attr_timing_master);
+ if (ret) {
+ dev_info(&wc->xb.pdev->dev,
+ "Failed to create device attributes.\n");
+ }
+
+ dev_warn(&wc->xb.pdev->dev, "WARNING: Creating dcxo file. Do not release like this.\n");
+ ret = device_create_file(&wc->xb.pdev->dev, &dev_attr_dcxo);
+ if (ret) {
+ dev_info(&wc->xb.pdev->dev,
+ "Failed to create DCXO device attributes.\n");
+ }
+}
+
+static void remove_sysfs_files(struct t43x *wc)
+{
+ device_remove_file(&wc->xb.pdev->dev, &dev_attr_timing_master);
+ device_remove_file(&wc->xb.pdev->dev, &dev_attr_dcxo);
+}
+
+static inline void __t43x_update_timing(struct t43x *wc)
+{
+ int i;
+
+ /* update sync src info */
+ if (wc->syncsrc != syncsrc) {
+ dev_info(&wc->xb.pdev->dev, "Swapping card %d from %d to %d\n",
+ wc->num, wc->syncsrc, syncsrc);
+ wc->syncsrc = syncsrc;
+ /* Update sync sources */
+ for (i = 0; i < wc->numspans; i++)
+ wc->tspans[i]->span.syncsrc = wc->syncsrc;
+ if (syncnum == wc->num) {
+ __t43x_set_rclk_src(wc, syncspan-1);
+ __t43x_set_sclk_src(wc, WCXB_CLOCK_RECOVER, 1);
+ if (debug) {
+ dev_notice(&wc->xb.pdev->dev,
+ "Card %d, using sync span %d, master\n",
+ wc->num, syncspan);
+ }
+ } else {
+ __t43x_set_sclk_src(wc, WCXB_CLOCK_SLAVE, 0);
+ if (debug) {
+ dev_notice(&wc->xb.pdev->dev,
+ "Card %d, using Timing Bus, NOT master\n",
+ wc->num);
+ }
+ }
+ }
+}
+
+static int __t43x_findsync(struct t43x *wc)
+{
+ int i;
+ unsigned long flags;
+ int p;
+ int nonzero;
+ int newsyncsrc = 0; /* DAHDI span number */
+ int newsyncnum = 0; /* wct4xxp card number */
+ int newsyncspan = 0; /* span on given wct4xxp card */
+ struct t43x *cur;
+
+ spin_lock_irqsave(&synclock, flags);
+ if (!wc->num) {
+ /* If we're the first card, go through all the motions, up to 8
+ * levels of sync source */
+ p = 1;
+ while (p < 8) {
+ nonzero = 0;
+ list_for_each_entry(cur, &card_list, card_node) {
+ for (i = 0; i < cur->numspans; i++) {
+ struct t43x_span *const ts =
+ cur->tspans[i];
+ struct dahdi_span *const s =
+ &cur->tspans[i]->span;
+ if (!ts->syncpos)
+ continue;
+ nonzero = 1;
+ if ((ts->syncpos == p) &&
+ !(s->alarms & NOSYNC_ALARMS) &&
+ (s->flags & DAHDI_FLAG_RUNNING)) {
+ /* This makes a good sync
+ * source */
+ newsyncsrc = s->spanno;
+ newsyncnum = cur->num;
+ newsyncspan = i + 1;
+ /* Jump out */
+ goto found;
+ }
+ }
+ }
+ if (nonzero)
+ p++;
+ else
+ break;
+ }
+found:
+ if ((syncnum != newsyncnum) ||
+ (syncsrc != newsyncsrc) ||
+ (newsyncspan != syncspan)) {
+ if (debug) {
+ dev_notice(&wc->xb.pdev->dev,
+ "New syncnum: %d (was %d), syncsrc: %d (was %d), syncspan: %d (was %d)\n",
+ newsyncnum, syncnum, newsyncsrc,
+ syncsrc, newsyncspan, syncspan);
+ }
+ syncnum = newsyncnum;
+ syncsrc = newsyncsrc;
+ syncspan = newsyncspan;
+ nonzero = 0;
+ list_for_each_entry(cur, &card_list, card_node)
+ __t43x_update_timing(cur);
+ }
+ }
+ __t43x_update_timing(wc);
+ spin_unlock_irqrestore(&synclock, flags);
+ return 0;
+}
+
+static void __t43x_set_timing_source_auto(struct t43x *wc)
+{
+ int x, i;
+ int firstprio, secondprio;
+ firstprio = secondprio = 4;
+
+ if (debug)
+ dev_info(&wc->xb.pdev->dev, "timing source auto\n");
+
+ if (timingcable) {
+ __t43x_findsync(wc);
+ } else {
+ if (debug)
+ dev_info(&wc->xb.pdev->dev,
+ "Evaluating spans for timing source\n");
+ for (x = 0; x < wc->numspans; x++) {
+ if ((wc->tspans[x]->span.flags & DAHDI_FLAG_RUNNING) &&
+ !(wc->tspans[x]->span.alarms & (DAHDI_ALARM_RED |
+ DAHDI_ALARM_BLUE))) {
+ if (debug) {
+ dev_info(&wc->xb.pdev->dev,
+ "span %d is green : syncpos %d\n",
+ x+1, wc->tspans[x]->syncpos);
+ }
+ if (wc->tspans[x]->syncpos) {
+ /* Valid rsync source in recovered
+ timing mode */
+ if (firstprio == 4)
+ firstprio = x;
+ else if (wc->tspans[x]->syncpos <
+ wc->tspans[firstprio]->syncpos)
+ firstprio = x;
+ } else {
+ /* Valid rsync source in system timing
+ mode */
+ if (secondprio == 4)
+ secondprio = x;
+ }
+ }
+ }
+ if (firstprio != 4) {
+ wc->syncsrc = firstprio;
+ __t43x_set_rclk_src(wc, firstprio);
+ __t43x_set_sclk_src(wc, WCXB_CLOCK_RECOVER, 0);
+ dev_info(&wc->xb.pdev->dev,
+ "Recovered timing mode, RCLK set to span %d\n",
+ firstprio+1);
+ } else if (secondprio != 4) {
+ wc->syncsrc = -1;
+ __t43x_set_rclk_src(wc, secondprio);
+ __t43x_set_sclk_src(wc, WCXB_CLOCK_SELF, 0);
+ dev_info(&wc->xb.pdev->dev,
+ "System timing mode, RCLK set to span %d\n",
+ secondprio+1);
+ } else {
+ wc->syncsrc = -1;
+ dev_info(&wc->xb.pdev->dev,
+ "All spans in alarm : No valid span to source RCLK from\n");
+ /* Default rclk to lock with span 1 */
+ __t43x_set_rclk_src(wc, 0);
+ __t43x_set_sclk_src(wc, WCXB_CLOCK_SELF, 0);
+ }
+
+ /* Propagate sync selection to dahdi_span struct
+ * this is read by dahdi_tool to display the span's
+ * master/slave sync information */
+ for (i = 0; i < wc->numspans; i++)
+ wc->tspans[i]->span.syncsrc = wc->syncsrc + 1;
+ }
+}
+
+static void
+t43x_configure_t1(struct t43x *wc, int span_idx, int lineconfig, int txlevel)
+{
+ struct t43x_span *ts = wc->tspans[span_idx];
+ int fidx = (wc->numspans == 2) ? span_idx+1 : span_idx;
+ unsigned int fmr4, fmr2, fmr1, fmr0, lim2;
+ char *framing, *line;
+ int mytxlevel, reg;
+ unsigned long flags;
+
+ if ((txlevel > 7) || (txlevel < 4))
+ mytxlevel = 0;
+ else
+ mytxlevel = txlevel - 4;
+
+ /* FMR1: Mode 0, T1 mode, CRC on for ESF, 8.192 Mhz system data rate,
+ * no XAIS */
+ fmr1 = 0x9c;
+ /* FMR2: no payload loopback, don't auto yellow alarm */
+ fmr2 = 0x20;
+
+ if (SPANTYPE_DIGITAL_J1 == ts->span.spantype) {
+ fmr4 = 0x1c;
+ } else {
+ /* FMR4: Lose sync on 2 out of 5 framing bits, auto resync */
+ fmr4 = 0x0c;
+ }
+
+ /* LIM2: 50% peak is a "1", Advanced Loss Recovery, Multi Purpose
+ * Analog Switch enabled */
+ lim2 = 0x23;
+ /* LIM2: Add line buildout */
+ lim2 |= (mytxlevel << 6);
+
+ spin_lock_irqsave(&wc->reglock, flags);
+
+ __t43x_framer_set(wc, fidx, 0x1d, fmr1);
+ __t43x_framer_set(wc, fidx, 0x1e, fmr2);
+
+ /* Configure line interface */
+ if (lineconfig & DAHDI_CONFIG_AMI) {
+ line = "AMI";
+ /* WCT4XX has workaround for errata fmr0 = 0xb0 */
+ /* was fmr0 = 0xa0; */
+ fmr0 = 0xb0;
+ } else {
+ line = "B8ZS";
+ fmr0 = 0xf0;
+ }
+ if (lineconfig & DAHDI_CONFIG_D4) {
+ framing = "D4";
+ } else {
+ framing = "ESF";
+ fmr4 |= 0x2;
+ fmr2 |= 0xc0;
+ }
+
+ /* Suppress RSC interrupt for cleared channels */
+ __t43x_framer_set(wc, fidx, 0x09, 0x80);
+ __t43x_framer_set(wc, fidx, 0x1c, fmr0);
+
+ __t43x_framer_set(wc, fidx, 0x20, fmr4);
+ /* FMR5: Enable RBS mode */
+ __t43x_framer_set(wc, fidx, 0x21, 0x40);
+
+ /* LIM1: Clear data in case of LOS, Set receiver threshold (0.5V), No
+ * remote loop, no DRS */
+ __t43x_framer_set(wc, fidx, 0x37, 0xf0);
+ /* LIM0: Enable auto long haul mode, no local loop (set after LIM1) */
+ __t43x_framer_set(wc, fidx, 0x36, 0x08);
+
+ /* CMDR: Reset the receiver and transmitter line interface */
+ __t43x_framer_set(wc, fidx, 0x02, 0x50);
+ /* CMDR: Reset the receiver and transmitter line interface */
+ __t43x_framer_set(wc, fidx, 0x02, 0x00);
+ if (debug) {
+ dev_info(&wc->xb.pdev->dev,
+ "card %d span %d: setting Rtx to 0ohm for T1\n",
+ wc->num, span_idx);
+ }
+ /* PC6: set Rtx to 0ohm for T1 */
+ __t43x_framer_set(wc, fidx, 0x86, 0x00);
+
+ /* Bugfix register for errata #3 */
+ __t43x_framer_set(wc, fidx, 0xbd, 0x05);
+
+ /* LIM2: 50% peak amplitude is a "1" */
+ __t43x_framer_set(wc, fidx, 0x3a, lim2);
+ /* PCD: LOS after 176 consecutive "zeros" */
+ __t43x_framer_set(wc, fidx, 0x38, 0x0a);
+ /* PCR: 22 "ones" clear LOS */
+ __t43x_framer_set(wc, fidx, 0x39, 0x15);
+
+ reg = __t43x_framer_get(wc, fidx, 0x24);
+ if (SPANTYPE_DIGITAL_J1 == ts->span.spantype) {
+ /* set J1 overide */
+ __t43x_framer_set(wc, fidx, 0x24, reg | 0x80);
+ } else {
+ /* clear J1 overide */
+ __t43x_framer_set(wc, fidx, 0x24, reg & ~0x80);
+ }
+
+ /* Generate pulse mask for T1 */
+ switch (mytxlevel) {
+ case 3:
+ __t43x_framer_set(wc, fidx, 0x26, 0x07); /* XPM0 */
+ __t43x_framer_set(wc, fidx, 0x27, 0x01); /* XPM1 */
+ __t43x_framer_set(wc, fidx, 0x28, 0x00); /* XPM2 */
+ break;
+ case 2:
+ __t43x_framer_set(wc, fidx, 0x26, 0x8c); /* XPM0 */
+ __t43x_framer_set(wc, fidx, 0x27, 0x11); /* XPM1 */
+ __t43x_framer_set(wc, fidx, 0x28, 0x01); /* XPM2 */
+ break;
+ case 1:
+ __t43x_framer_set(wc, fidx, 0x26, 0x8c); /* XPM0 */
+ __t43x_framer_set(wc, fidx, 0x27, 0x01); /* XPM1 */
+ __t43x_framer_set(wc, fidx, 0x28, 0x00); /* XPM2 */
+ break;
+ case 0:
+ default:
+ __t43x_framer_set(wc, fidx, 0x26, 0x1a); /* XPM0 */
+ __t43x_framer_set(wc, fidx, 0x27, 0x27); /* XPM1 */
+ __t43x_framer_set(wc, fidx, 0x28, 0x01); /* XPM2 */
+ break;
+ }
+
+ __t43x_framer_set(wc, fidx, 0x14, 0xff); /* IMR0 */
+ __t43x_framer_set(wc, fidx, 0x15, 0xff); /* IMR1 */
+
+ /* IMR2: All the alarms */
+ __t43x_framer_set(wc, fidx, 0x16, 0x00);
+ /* IMR3: ES, SEC, LLBSC, rx slips */
+ __t43x_framer_set(wc, fidx, 0x17, 0x34);
+ /* IMR4: Slips on transmit */
+ __t43x_framer_set(wc, fidx, 0x18, 0x3f);
+
+ spin_unlock_irqrestore(&wc->reglock, flags);
+ dev_info(&wc->xb.pdev->dev, "Span %d configured for %s/%s\n",
+ span_idx, framing, line);
+}
+
+static void t43x_configure_e1(struct t43x *wc, int span_idx, int lineconfig)
+{
+ int fidx = (wc->numspans == 2) ? span_idx+1 : span_idx;
+ unsigned int fmr2, fmr1, fmr0;
+ unsigned int cas = 0;
+ unsigned int imr3extra = 0;
+ char *crc4 = "";
+ char *framing, *line;
+ unsigned long flags;
+
+ fmr1 = 0x44; /* FMR1: E1 mode, Automatic force resync, PCM30 mode,
+ 8.192 Mhz backplane, no XAIS */
+ fmr2 = 0x03; /* FMR2: Auto transmit remote alarm, auto loss of
+ multiframe recovery, no payload loopback */
+
+ if (lineconfig & DAHDI_CONFIG_CRC4) {
+ fmr1 |= 0x08; /* CRC4 transmit */
+ fmr2 |= 0xc0; /* CRC4 receive */
+ crc4 = "/CRC4";
+ }
+
+ spin_lock_irqsave(&wc->reglock, flags);
+
+ __t43x_framer_set(wc, fidx, 0x1d, fmr1);
+ __t43x_framer_set(wc, fidx, 0x1e, fmr2);
+
+ /* Configure line interface */
+ if (lineconfig & DAHDI_CONFIG_AMI) {
+ line = "AMI";
+ /* workaround for errata #2 in ES v3 09-10-16 */
+ fmr0 = 0xb0;
+ } else {
+ line = "HDB3";
+ fmr0 = 0xf0;
+ }
+
+ if (lineconfig & DAHDI_CONFIG_CCS) {
+ framing = "CCS";
+ imr3extra = 0x28;
+ } else {
+ framing = "CAS";
+ cas = 0x40;
+ }
+
+ __t43x_framer_set(wc, fidx, 0x1c, fmr0);
+
+ /* LIM1: Clear data in case of LOS, Set receiver threshold (0.5V), No
+ * remote loop, no DRS */
+ __t43x_framer_set(wc, fidx, 0x37, 0xf0);
+ /* LIM0: Enable auto long haul mode, no local loop (must be after
+ * LIM1) */
+ __t43x_framer_set(wc, fidx, 0x36, 0x08);
+
+ /* CMDR: Reset the receiver and transmitter line interface */
+ __t43x_framer_set(wc, fidx, 0x02, 0x50);
+ /* CMDR: Reset the receiver and transmitter line interface */
+ __t43x_framer_set(wc, fidx, 0x02, 0x00);
+ if (debug)
+ dev_info(&wc->xb.pdev->dev,
+ "setting Rtx to 7.5ohm for E1\n");
+ /* PC6: turn on 7.5ohm Rtx for E1 */
+ __t43x_framer_set(wc, fidx, 0x86, 0x40);
+
+ /* Condition receive line interface for E1 after reset */
+ __t43x_framer_set(wc, fidx, 0xbb, 0x17);
+ __t43x_framer_set(wc, fidx, 0xbc, 0x55);
+ __t43x_framer_set(wc, fidx, 0xbb, 0x97);
+ __t43x_framer_set(wc, fidx, 0xbb, 0x11);
+ __t43x_framer_set(wc, fidx, 0xbc, 0xaa);
+ __t43x_framer_set(wc, fidx, 0xbb, 0x91);
+ __t43x_framer_set(wc, fidx, 0xbb, 0x12);
+ __t43x_framer_set(wc, fidx, 0xbc, 0x55);
+ __t43x_framer_set(wc, fidx, 0xbb, 0x92);
+ __t43x_framer_set(wc, fidx, 0xbb, 0x0c);
+ __t43x_framer_set(wc, fidx, 0xbb, 0x00);
+ __t43x_framer_set(wc, fidx, 0xbb, 0x8c);
+
+ /* LIM2: 50% peak amplitude isa "1", Multi Purpose Analog Switch
+ * enabled */
+ __t43x_framer_set(wc, fidx, 0x3a, 0x22);
+
+ /* PCD: LOS after 176 consecutive "zeros" */
+ __t43x_framer_set(wc, fidx, 0x38, 0x0a);
+ /* PCR: 22 "ones" clear LOS */
+ __t43x_framer_set(wc, fidx, 0x39, 0x15);
+
+ /* XSW: Spare bits all to 1 */
+ __t43x_framer_set(wc, fidx, 0x20, 0x9f);
+ /* XSP: E-bit set when async. AXS auto, XSIF to 1 */
+ __t43x_framer_set(wc, fidx, 0x21, 0x1c|cas);
+
+ /* Generate pulse mask for E1 */
+ __t43x_framer_set(wc, fidx, 0x26, 0x74); /* XPM0 */
+ __t43x_framer_set(wc, fidx, 0x27, 0x02); /* XPM1 */
+ __t43x_framer_set(wc, fidx, 0x28, 0x00); /* XPM2 */
+
+ __t43x_framer_set(wc, fidx, 0x14, 0xff); /* IMR0 */
+ __t43x_framer_set(wc, fidx, 0x15, 0xff); /* IMR1 */
+
+ __t43x_framer_set(wc, fidx, 0x16, 0x00); /* IMR2: the alarm stuff! */
+ __t43x_framer_set(wc, fidx, 0x17, 0x04 | imr3extra); /* IMR3: AIS */
+ __t43x_framer_set(wc, fidx, 0x18, 0x3f); /* IMR4: slips on transmit */
+
+ spin_unlock_irqrestore(&wc->reglock, flags);
+ dev_info(&wc->xb.pdev->dev, "Span configured for %s/%s%s\n",
+ framing, line, crc4);
+}
+
+static void t43x_framer_start(struct t43x *wc)
+{
+ int unit;
+ struct t43x_span *ts;
+ unsigned long flags;
+ int res;
+
+ if (debug)
+ dev_info(&wc->xb.pdev->dev, "%s\n", __func__);
+
+ /* Disable fpga hardware interrupts */
+ wcxb_disable_interrupts(&wc->xb);
+
+ /* Disable DMA */
+ wcxb_stop_dma(&wc->xb);
+ res = wcxb_wait_for_stop(&wc->xb, 50);
+ if (res)
+ dev_warn(&wc->xb.pdev->dev, "DMA engine did not stop.\n");
+
+ for (unit = 0; unit < wc->numspans; unit++) {
+ ts = wc->tspans[unit];
+ if (dahdi_is_e1_span(&ts->span)) {
+ t43x_configure_e1(wc, unit, ts->span.lineconfig);
+ } else { /* is a T1 card */
+ t43x_configure_t1(wc, unit, ts->span.lineconfig,
+ ts->span.txlevel);
+ }
+ t43x_set_cas_mode(wc, unit);
+
+ set_bit(DAHDI_FLAGBIT_RUNNING, &ts->span.flags);
+ }
+
+ for (unit = 0; unit < wc->numspans; unit++) {
+ /* Get this party started */
+ local_irq_save(flags);
+ t43x_check_alarms(wc, unit);
+ t43x_check_sigbits(wc, unit);
+ local_irq_restore(flags);
+ }
+
+ dev_info(&wc->xb.pdev->dev, "Enabling DMA controller and interrupts\n");
+
+ /* start interrupts and DMA processing */
+ wcxb_start(&wc->xb);
+
+ t43x_check_for_interrupts(wc);
+
+ /* force re-evaluation of timing source */
+ wc->syncsrc = -1;
+ spin_lock_irqsave(&wc->reglock, flags);
+ __t43x_set_timing_source_auto(wc);
+ spin_unlock_irqrestore(&wc->reglock, flags);
+
+ /* Clear all counters */
+ for (unit = 0; unit < wc->numspans; unit++) {
+ ts = wc->tspans[unit];
+ memset(&ts->span.count, 0, sizeof(ts->span.count));
+ }
+
+ /* Invoke timer function to set leds */
+ mod_timer(&wc->timer, jiffies);
+}
+
+#ifndef RPC_RCLK
+/**
+ * t43x_check_spanconfig - Return 0 if the span configuration is valid.
+ * @wc - The card to check.
+ *
+ * The TE435 cannot sync timing from a span in a different line mode than the
+ * first span. This function should be called after the spans are configured to
+ * ensure that the are not configured in this mode.
+ *
+ */
+static int t43x_check_spanconfig(const struct t43x *wc)
+{
+ unsigned int i;
+ bool span_1_is_e1;
+
+ if (&te435 != wc->devtype)
+ return 0;
+
+ span_1_is_e1 = dahdi_is_e1_span(&wc->tspans[0]->span);
+
+ for (i = 1; i < wc->numspans; ++i) {
+ struct t43x_span *ts = wc->tspans[i];
+
+ /* We only need to check spans that we could be a sync source */
+ if (!ts->syncpos)
+ continue;
+
+ if ((bool)dahdi_is_e1_span(&ts->span) == span_1_is_e1)
+ continue;
+
+ dev_warn(&wc->xb.pdev->dev,
+ "Local span %d is configured as a sync source but the line mode does not match local span 1.\n",
+ ts->span.offset + 1);
+ dev_warn(&wc->xb.pdev->dev,
+ "Please configure local span 1 as a sync src and ensure all other local sync sources match the line config of span 1.\n");
+
+ return -EINVAL;
+ }
+
+ return 0;
... 13676 lines suppressed ...
--
dahdi/linux.git
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