[dahdi-commits] tzafrir: linux/trunk r5320 - /linux/trunk/drivers/dahdi/xpp/
SVN commits to the DAHDI project
dahdi-commits at lists.digium.com
Mon Nov 17 12:01:47 CST 2008
Author: tzafrir
Date: Mon Nov 17 12:01:47 2008
New Revision: 5320
URL: http://svn.digium.com/view/dahdi?view=rev&rev=5320
Log:
xpp_pri: Fix T1 CRC initialization
Clock synchronization when sync is not from first port.
Modified:
linux/trunk/drivers/dahdi/xpp/card_pri.c
linux/trunk/drivers/dahdi/xpp/init_card_4_30
Modified: linux/trunk/drivers/dahdi/xpp/card_pri.c
URL: http://svn.digium.com/view/dahdi/linux/trunk/drivers/dahdi/xpp/card_pri.c?view=diff&rev=5320&r1=5319&r2=5320
==============================================================================
--- linux/trunk/drivers/dahdi/xpp/card_pri.c (original)
+++ linux/trunk/drivers/dahdi/xpp/card_pri.c Mon Nov 17 12:01:47 2008
@@ -203,7 +203,8 @@
#define REG_FMR1_XAIS BIT(0) /* Transmit AIS toward transmit end */
#define REG_FMR1_SSD0 BIT(1)
#define REG_FMR1_ECM BIT(2)
-#define REG_FMR1_XFS BIT(3) /* Transmit Framing Select */
+#define REG_FMR1_T_CRC BIT(3) /* Enable CRC6 */
+#define REG_FMR1_E_XFS BIT(3) /* Transmit Framing Select */
#define REG_FMR1_PMOD BIT(4) /* E1 = 0, T1/J1 = 1 */
#define REG_FMR1_EDL BIT(5)
#define REG_FMR1_AFR BIT(6)
@@ -275,6 +276,15 @@
#define REG_RS14_E 0x7D /* Receive CAS Register 14 */
#define REG_RS15_E 0x7E /* Receive CAS Register 15 */
#define REG_RS16_E 0x7F /* Receive CAS Register 16 */
+
+#define REG_PC2 0x81 /* Port Configuration 2 */
+#define REG_PC3 0x82 /* Port Configuration 3 */
+#define REG_PC4 0x83 /* Port Configuration 4 */
+
+#define VAL_PC_SYPR 0x00 /* Synchronous Pulse Receive (Input, low active) */
+#define VAL_PC_GPI 0x90 /* General purpose input */
+#define VAL_PC_GPOH 0x0A /* General Purpose Output, high level */
+#define VAL_PC_GPOL 0x0B /* General Purpose Output, low level */
#define NUM_CAS_RS (REG_RS16_E - REG_RS2_E + 1)
@@ -367,7 +377,7 @@
regnum, val);
return xpp_register_request(
xpd->xbus, xpd,
- PRI_PORT(xpd), /* portno */
+ 0, /* portno=0 */
1, /* writing */
regnum,
0, /* do_subreg */
@@ -600,13 +610,16 @@
}
/* Now set it */
if(best_xpd && ((struct PRI_priv_data *)(best_xpd->priv))->clock_source == 0) {
- byte cmr1_val =
- REG_CMR1_RS |
- REG_CMR1_STF |
- (REG_CMR1_DRSS & (best_subunit << 6));
- XPD_DBG(SYNC, best_xpd,
- "ClockSource Set: cmr1=0x%02X\n", cmr1_val);
- pri_write_reg(xpd, REG_CMR1, cmr1_val);
+ byte reg_pc_init[] = { VAL_PC_SYPR, VAL_PC_GPI, VAL_PC_GPI };
+
+ for(i = 0; i < ARRAY_SIZE(reg_pc_init); i++) {
+ byte reg_pc = reg_pc_init[i];
+
+ reg_pc |= (best_subunit & (1 << i)) ? VAL_PC_GPOH : VAL_PC_GPOL;
+ XPD_DBG(SYNC, best_xpd,
+ "ClockSource Set: PC%d=0x%02X\n", 2+i, reg_pc);
+ pri_write_reg(xpd, REG_PC2 + i, reg_pc);
+ }
((struct PRI_priv_data *)(best_xpd->priv))->clock_source = 1;
}
/* clear old clock sources */
@@ -758,7 +771,7 @@
fmr4 = 0x9F; /* E1.XSW: All spare bits = 1*/
xsp |= REG_XSP_E_EBP | REG_XSP_E_AXS | REG_XSP_E_XSIF;
} else if(priv->pri_protocol == PRI_PROTO_T1) {
- fmr1 |= REG_FMR1_PMOD;
+ fmr1 |= REG_FMR1_PMOD | REG_FMR1_T_CRC;
fmr2 = REG_FMR2_T_SSP | REG_FMR2_T_AXRA; /* 0x22 */
fmr4 = 0x0C;
xsp |= REG_FMR5_T_XTM;
@@ -804,10 +817,14 @@
priv->is_cas = 1;
}
pri_pcm_update(xpd);
- /* E1's can enable CRC checking */
+ /*
+ * E1's can enable CRC checking
+ * CRC4 is legal only for E1, and it is checked by pri_linecompat()
+ * in the beginning of the function.
+ */
if (lineconfig & DAHDI_CONFIG_CRC4) {
crcstr = "CRC4";
- fmr1 |= REG_FMR1_XFS;
+ fmr1 |= REG_FMR1_E_XFS;
fmr2 |= REG_FMR2_E_RFS1;
fmr3 |= REG_FMR3_EXTIW;
}
@@ -1289,7 +1306,7 @@
spin_unlock_irqrestore(&xpd->lock, flags);
LINE_DBG(SIGNAL, xpd, pos, "RBS: TX: bits=0x%X (reg=0x%X val=0x%02X)\n",
bits, regnum, val);
- pri_write_reg(xpd, regnum, val);
+ write_subunit(xpd, regnum, val);
return 0;
}
Modified: linux/trunk/drivers/dahdi/xpp/init_card_4_30
URL: http://svn.digium.com/view/dahdi/linux/trunk/drivers/dahdi/xpp/init_card_4_30?view=diff&rev=5320&r1=5319&r2=5320
==============================================================================
--- linux/trunk/drivers/dahdi/xpp/init_card_4_30 (original)
+++ linux/trunk/drivers/dahdi/xpp/init_card_4_30 Mon Nov 17 12:01:47 2008
@@ -129,6 +129,10 @@
sub init_quad() {
main::select_subunit(0);
+
+ PRI::gen "0 WD D6 20"; # GPC6.COMP_DIS=1
+ # (Compatibility Mode Disable)
+
# Tuning of clocking unit to the 16.384 MHz reference frequence
# by setting Global Clock Mode registers (GCM[1:8]), same for E1 and T1/J1
PRI::gen "0 WD 92 00"; # GCM1
@@ -162,9 +166,6 @@
PRI::gen "0 WD BC 00"; # REGFD
# PRI::gen "0 WD 80 00"; # PC1 (Port configuration 1): RPB_1.SYPR , XPB_1.SYPX
- PRI::gen "0 WD 81 0B"; # PC2 (Port configuration 2): RPB_1.GPOH (ResetID ), XPB_1.GPOL (MUX_SEL0)
- PRI::gen "0 WD 82 9B"; # PC3 (Port configuration 3): RPC_1.GPI (nConfig0), XPC_1.GPOL (MUX_SEL1)
- PRI::gen "0 WD 83 9B"; # PC4 (Port configuration 4): RPD_1.GPI (nConfig1), XPD_1.GPOL (MUX_SEL2)
}
sub read_defaults() {
@@ -233,9 +234,9 @@
my $port = shift;
my $portno = $port->{PORT_NUM};
- # only one of the following loopbacks can be activated in the same time
- my $LIM1_RL = 0 << 1; # RL (Remote Loopback)
- my $lim1 = 0xB0 | $LIM1_RL;
+ my $cmr5 = sprintf("%x", ($portno << 5));
+
+ PRI::gen "$portno WD 42 $cmr5"; # CMR5.DRSS=portno
PRI::gen "$portno WD 26 F6"; # XPM0: Pulse Shape Programming for R1=18Ohms
PRI::gen "$portno WD 27 02"; # XPM1: ...3V Pulse Level at the line (Vp-p=6v)
@@ -255,6 +256,9 @@
# PRI::gen "0 WD 1F 20"; # LOOP (Channel Looback):
#}
+ # only one of the following loopbacks can be activated in the same time
+ my $LIM1_RL = 0 << 1; # RL (Remote Loopback)
+ my $lim1 = 0xB0 | $LIM1_RL;
PRI::gen "$portno WD 37 %02X", $lim1;
# LIM1: ~RL (Remote Loop bit 0x02),
# ~DRS (Dual Rail Select, latch receive data while trasmit),
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