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<blockquote class="gmail_quote" style="PADDING-LEFT: 1ex; MARGIN: 0px 0px 0px 0.8ex; BORDER-LEFT: #ccc 1px solid"><br>For something like G.729 encode/decode a direct comparison between a<br>processor on a card and host processing comes down to a 1:1 comparison<br>
of their processing performance (not their MIPS - a customised DSP<br>processor's instructions typically do the work of several general<br>purpose processor instructions, and quality of match between the working<br>set and the cache size has a huge (10-20 fold) impact on speed on a<br>
Pentium class processor). Echo cancellation is a special case. The<br>adaption process in an echo cancellor is a control loop, and it gets<br>bogged down in latency issues when run on the host processor. To keep<br>the signal latency low means loosing most of the benefits of PCI bus<br>
mastering (those nasty 1ms chunks that many cards work in), and<br>suffering enormous context switching overheads.</blockquote>
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<div>That`s my point... using an exclusive core as data handler, and running only this task to minimize context switching, we could take care of 8x faster interrupts didn`t we ? </div>
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<div>PCI overhead will increase, but I don`t think it would be a problem. We are talking about 120 channels * 64kbits/s (8kbytes/s) = 960kbytes/sec ... </div>
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<div>Well, let me study a little bit more about the subject.... may be I need not a symetrical (SMP) multiprocessor support but something assymetrical... </div>
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<div>Luis A P Barbosa</div>
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