[Asterisk-Dev] Wildcard TE410P Question

[Steve Underwood]

Paul Cadach wrote:

>Hello,
>
><creslin at digium.com> wrote:
>  
>
>>I know that the framer does support some primitives
>>for doing SS7 signalling, but I do not they are enabled by default in the driver
>>for the TE410P.
>>    
>>
>
>Framer used in TE405P/TE410P have builtin SS7-capable HDLC controller which COULDN'T be used by current HARDWARE design
>in bus-mastering mode, only  by regular polling of framer's registers.
>  
>
Correct. The card's hardware design precludes the use of the hardware 
HDLC controller. However, this isn't really a problem when you only want 
to use one 64K slot for HDLC.

In our SS7 software for the TE405P/TE410P cards and Asterisk, we use the 
software HDLC built into the zaptel drivers, and deal with MTP and the 
higher layers in our userland code. The only problem with this, is the 
flood of FISU messages (tiny messages which occupy all idle time on SS7 
links), as there are so many. We modified the zaptel driver to mitigate 
this flood.

Another workable strategy would be to operate the zaptel driver in clear 
mode for the signalling channel, and do the HDLC stuffing in userland. 
Then you only need to deal with 50x20ms blocks of data per second.

Regards,
Steve