[Asterisk-Dev] X101P register map data please?

[Mark Burton]

On 15 Aug 2005, at 23:46, Martin Harriss wrote:

> I think this might help:
>
> http://www.tjnet.com/software/download/data_sheets/ 
> Tiger320_data_sheet.pdf
>

you are fantastic, thanks!

I think I am almost there with a very simple solution, BUT, I seem to  
have a problem which MAY be totally unrelated.

I have a patch which does what this piece of text says to do..

In the event that the PCI bus master logic detects an abort condition,  
Interrupt 0 status register  (Index 0x6) bit 4 and 5 will be set based  
on the abort condition. It can be cleared by reading the  status  
register. To recover the PCI master state machine, set the reset bit in  
register 0 to 1 and  reset it to 0, also enable the DMA operation by  
setting register 1 bit 0 to 1.

here's my code...
                outb(0x03, wc->ioaddr + WC_CNTL);
                 outb(0x01, wc->ioaddr + WC_CNTL);

                 outb(0x01, wc->ioaddr + WC_OPER);

The IRQ routine already reads the status register

So. This would seem to be a solution.

In my system, it seems to work, in that, when I get a PCI abort, it is  
handled, and things continue... - but here's the rub, it's not exactly  
100% working!

The symptoms of it's failing are that after about 10 min's or so of  
"activity" on the machine, zttest starts to report %;s around about 0  
!!!!!
	Thats not good, but strangely, it seems to be totally unrelated to any  
PCI Abort event, so I dont understand it...
		When this happens, voice quality across the zap channel dies... And  
the situation is not recoverable (or at least I can't find a way of  
recovering it), unless you unload and reload the modules...

So. Before I offer this as a patch, I need to get to the bottom of this  
"other" problem
	
Anybody seen anything like it before?

Cheers

Mark.



> You might also need the SLIC data sheet from Silicon Labs, not sure  
> about that...
>
> Martin
>
>
> Mark Burton wrote:
>> Hi, I've been trying to debug the problem with the X101P  giving FXO  
>> PCI Master Aborts... I'm doing this blind, and I really need some  
>> info on the X101P's register map - or best of all, the conditions  
>> under which it can generate an IRQ with a mask of 0x10.
>> I have so far set up the mask for the IRQ's in the interrupt handler  
>> (so the poor thing doesn't keep getting them)[as per previous post],  
>> then patched ztcfg so it actually starts the watchdog (which is  
>> assumed by the driver, but in reality doesn't happen - of course it  
>> doesn't need to, because under normal conditions there is no need for  
>> the watchdog - I guess?)
>> That much gives me a system which runs, hits a PCI Master abort (or  
>> at least an IRQ with a mask of 0x10), and then stops the dma, masks  
>> the IRQ... then the watchdog starts the dma again, unmasks the IRQ,  
>> at which point  it gets another IRQ before the next watchdog beat....  
>> so the watchdog can't help.
>> I have tried being a bit more brutal with the activities in the  
>> watchdog routine.... I just caused myself some kernel panic's :-)
>> Again, any help appreciated!
>> Cheers
>> Mark.
>> _______________________________________________
>> Asterisk-Dev mailing list
>> Asterisk-Dev at lists.digium.com
>> http://lists.digium.com/mailman/listinfo/asterisk-dev
>> To UNSUBSCRIBE or update options visit:
>>   http://lists.digium.com/mailman/listinfo/asterisk-dev
>
> _______________________________________________
> Asterisk-Dev mailing list
> Asterisk-Dev at lists.digium.com
> http://lists.digium.com/mailman/listinfo/asterisk-dev
> To UNSUBSCRIBE or update options visit:
>   http://lists.digium.com/mailman/listinfo/asterisk-dev
>