[asterisk-bugs] [DAHDI-linux 0015261]: [patch] SPI clock timing to SI3210/15 is not as per datasheet

Asterisk Bug Tracker noreply at bugs.digium.com
Tue Sep 15 15:52:24 CDT 2009


A NOTE has been added to this issue. 
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https://issues.asterisk.org/view.php?id=15261 
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Reported By:                alecdavis
Assigned To:                sruffell
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Project:                    DAHDI-linux
Issue ID:                   15261
Category:                   wctdm
Reproducibility:            always
Severity:                   tweak
Priority:                   normal
Status:                     acknowledged
Target Version:             2.2.0
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Date Submitted:             2009-06-03 04:39 CDT
Last Modified:              2009-09-15 15:52 CDT
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Summary:                    [patch] SPI clock timing to SI3210/15 is not as per
datasheet
Description: 
Referring to Silicon Labs Si3215 datasheet "Figure 7, SPI Timing Diagram",
and capturing SCS, SLCK, SDO, and SDI on a scope revealed some
discrepencies between data sheet and code.

The is true also of Zaptel Code.

The areas of concern are:
  1. Idle state of clock is shown in data sheet as logic 1, Both the
write_8bits and read_8bits have code to SCLK to 1 before CS goes low.
read_8bits has code to set SCLK to logic 0 after CS has gone high.

  2. In read_8bits the reading of SD0 should happen after rising edge of
clock.
Currently it's read immediatley after SCLK is driven low.

If the SCLK idle state of 0 was for safety reasons, what about SDO, it can
be either 0 or 1. I don't think this was the reason.

Would these fix the code in wctdm_voicedaa_check_hook
/* Try to track issues that plague slot one FXO's */

====================================================================== 

---------------------------------------------------------------------- 
 (0110742) svnbot (reporter) - 2009-09-15 15:52
 https://issues.asterisk.org/view.php?id=15261#c110742 
---------------------------------------------------------------------- 
Repository: dahdi
Revision: 7140

U   linux/trunk/drivers/dahdi/wctdm.c

------------------------------------------------------------------------
r7140 | dbailey | 2009-09-15 15:52:23 -0500 (Tue, 15 Sep 2009) | 12 lines

Change WCTDM SPI clock off state polarity and read timing

Change the off state of the SPI clock to high and provide more time for
data to
settle out on SPI reads.

(closes issue https://issues.asterisk.org/view.php?id=15261)
Reported by: alecdavis
Patches:
      wctdm_spi_clocking.diff2.txt uploaded by alecdavis (license 585)
Tested by: alecdavis, dbailey


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http://svn.digium.com/view/dahdi?view=rev&revision=7140 

Issue History 
Date Modified    Username       Field                    Change               
====================================================================== 
2009-09-15 15:52 svnbot         Checkin                                      
2009-09-15 15:52 svnbot         Note Added: 0110742                          
======================================================================




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