[asterisk-bugs] [DAHDI-linux 0015261]: [patch] SPI clock timing to SI3210/15 is not as per datasheet
Asterisk Bug Tracker
noreply at bugs.digium.com
Wed Jun 3 14:21:24 CDT 2009
A NOTE has been added to this issue.
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https://issues.asterisk.org/view.php?id=15261
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Reported By: alecdavis
Assigned To: sruffell
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Project: DAHDI-linux
Issue ID: 15261
Category: wctdm
Reproducibility: always
Severity: tweak
Priority: normal
Status: acknowledged
Target Version: 2.2.0
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Date Submitted: 2009-06-03 04:39 CDT
Last Modified: 2009-06-03 14:21 CDT
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Summary: [patch] SPI clock timing to SI3210/15 is not as per
datasheet
Description:
Referring to Silicon Labs Si3215 datasheet "Figure 7, SPI Timing Diagram",
and capturing SCS, SLCK, SDO, and SDI on a scope revealed some
discrepencies between data sheet and code.
The is true also of Zaptel Code.
The areas of concern are:
1. Idle state of clock is shown in data sheet as logic 1, Both the
write_8bits and read_8bits have code to SCLK to 1 before CS goes low.
read_8bits has code to set SCLK to logic 0 after CS has gone high.
2. In read_8bits the reading of SD0 should happen after rising edge of
clock.
Currently it's read immediatley after SCLK is driven low.
If the SCLK idle state of 0 was for safety reasons, what about SDO, it can
be either 0 or 1. I don't think this was the reason.
Would these fix the code in wctdm_voicedaa_check_hook
/* Try to track issues that plague slot one FXO's */
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(0105942) alecdavis (reporter) - 2009-06-03 14:21
https://issues.asterisk.org/view.php?id=15261#c105942
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In next day or so I'll be testing FXO to see if I can make the claim of
'found slot 1 FXO bug'
I need to know, the connection details for the modules, are the clock and
data in parallel, or does it use the daisy chain pass through method.
As SDI-SDO passthrough has a propagation delay, which may be relevant
here, which adds up as you go through each module.
Issue History
Date Modified Username Field Change
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2009-06-03 14:21 alecdavis Note Added: 0105942
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